From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Thu, 21 Aug 2014 19:01:17 +0200
Subject: [U-Boot] [PATCH v3 1/2] net: fec_mxc: Adjust RX DMA alignment
	for mx6solox
In-Reply-To: <CAOMZO5DNcV1M396vwcyez22NSBpmom4xZ0QGw6Fye6VhCLGPUw@mail.gmail.com>
References: <1408637529-31170-1-git-send-email-fabio.estevam@freescale.com>
	<201408211821.33065.marex@denx.de>
	<CAOMZO5DNcV1M396vwcyez22NSBpmom4xZ0QGw6Fye6VhCLGPUw@mail.gmail.com>
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On Thursday, August 21, 2014 at 06:41:26 PM, Fabio Estevam wrote:
> On Thu, Aug 21, 2014 at 1:21 PM, Marek Vasut <marex@denx.de> wrote:
> > Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't
> > there something completely else broken on MX6SX ?
> 
> Thanks for the review, Marek.
> 
> Inspecting this further I think the correct fix would be:
> 
>  arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
> b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 2631beb..e9e6f63 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -9,7 +9,7 @@
> 
>  #define ARCH_MXC
> 
> -#define CONFIG_SYS_CACHELINE_SIZE    32
> +#define CONFIG_SYS_CACHELINE_SIZE    64

Well yeah, it would ;-)

Best regards,
Marek Vasut