From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 2/3] pcie_imx: Add mx6solox support
Date: Mon, 25 Aug 2014 09:54:05 +0200 [thread overview]
Message-ID: <201408250954.05726.marex@denx.de> (raw)
In-Reply-To: <1408902746-12008-2-git-send-email-festevam@gmail.com>
On Sunday, August 24, 2014 at 07:52:25 PM, Fabio Estevam wrote:
[...]
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -504,10 +504,19 @@ int enable_pcie_clock(void)
> #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
> #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
> #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
> +#ifndef CONFIG_MX6SX
> + /* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */
> clrsetbits_le32(&anatop_regs->ana_misc1,
> ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
> ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
> ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
> +#else
> + /* lvds_clk1 is sourced from pcie ref on imx6sx */
> + clrsetbits_le32(&anatop_regs->ana_misc1,
> + ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
> + ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
> + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa);
> +#endif
Is that only 1-bit difference here ? What does the magic 0xa and 0xb stand for
please ?
> /* PCIe reference clock sourced from AXI. */
> clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
[...]
Best regards,
Marek Vasut
next prev parent reply other threads:[~2014-08-25 7:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-24 17:52 [U-Boot] [PATCH v2 1/3] mx6: imx-regs: Provide a structure for GPC registers Fabio Estevam
2014-08-24 17:52 ` [U-Boot] [PATCH v2 2/3] pcie_imx: Add mx6solox support Fabio Estevam
2014-08-25 7:54 ` Marek Vasut [this message]
2014-08-25 13:54 ` Fabio Estevam
2014-08-25 14:27 ` Marek Vasut
2014-08-25 17:29 ` Fabio Estevam
2014-08-24 17:52 ` [U-Boot] [PATCH v2 3/3] mx6sxsabresd: Add PCI support Fabio Estevam
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