[U-Boot] [PATCH v6 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Marek Vasut <marex@denx.de>]

On Saturday, August 23, 2014 at 02:41:50 PM, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
> Other SoCs work with the standard 32 bytes alignment.
> 
> Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
> which addresses the needs from mx6solox and also works for the other SoCs.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> Acked-by: Stefan Roese <sr@denx.de>
> ---
> Changes since v5:
> - Add Stefan's Ack
> Changes since v4:
> - None
> 
>  drivers/net/fec_mxc.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 4cefda4..56178d4 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR;
>   */
>  #define FEC_XFER_TIMEOUT	5000
> 
> +/*
> + * The standard 32-byte DMA alignment does not work on mx6solox, which
> requires + * 64-byte alignment in the DMA RX FEC buffer.
> + * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and
> also + * satisfies the alignment on other SoCs (32-bytes)
> + */
> +#define FEC_DMA_RX_MINALIGN	64
> +
>  #ifndef CONFIG_MII
>  #error "CONFIG_MII has to be defined!"
>  #endif
> @@ -286,7 +294,7 @@ static void fec_rbd_init(struct fec_priv *fec, int
> count, int dsize) * Reload the RX descriptors with default values and wipe
>  	 * the RX buffers.
>  	 */
> -	size = roundup(dsize, ARCH_DMA_MINALIGN);
> +	size = roundup(dsize, FEC_DMA_RX_MINALIGN);

This $size here is used only by the cache flushing functions. We agreed in the 
previous iterations, that the cacheline is 32b on MX6SX . This change is 
pointless unless ARCH_DMA_MINALIGN != 32 on MX6SX. Is that right ?
[...]

Best regards,
Marek Vasut