From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Date: Wed, 27 Aug 2014 15:28:06 +0200 Subject: [U-Boot] [PATCH 23/23] ARM: tegra: Enable PCIe on Jetson TK1 In-Reply-To: <53FC839A.7030108@nvidia.com> References: <1408346196-30419-1-git-send-email-thierry.reding@gmail.com> <1408346196-30419-24-git-send-email-thierry.reding@gmail.com> <53FC839A.7030108@nvidia.com> Message-ID: <20140827132800.GA32243@ulmo> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, Aug 26, 2014 at 03:54:50PM +0300, Tuomas Tynkkynen wrote: > On 18/08/14 10:16, Thierry Reding wrote: > [...] > > +static int as3722_gpio_direction_output(u8 gpio, u8 level) > > +{ > > + u8 value; > > + int err; > > + > > + if (gpio > 7) > > + return -EINVAL; > > + > > + if (level == 0) > > + value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL; > > + else > > + value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH; > > + > > + err = as3722_write(AS3722_GPIO_CONTROL(gpio), value); > > + if (err) { > > + error("as3722: failed to configure GPIO#%u as output: %d\n", > > + gpio, err); > > + return err; > > + } > > + > > + err = as3722_gpio_set(gpio, level); > > + if (err < 0) { > > + error("as3722: failed to set GPIO#%u high: %d\n", gpio, err); > > + return err; > > + } > > + > > + return 0; > > +} > > This function doesn't work correctly if the GPIO was originally configured > as inverted and low, which GPIO#2 seems to be. > (as3722_read(AS3722_GPIO_CONTROL(2), &value) returns value == 0x87)... That should be equivalent to what we're setting but is a somewhat weird default. I guess the fact that we're inverting it and then changing the value to high in separate transactions makes the output flip twice. > > + > > +int tegra_pcie_board_init(void) > > +{ > [...] > > + > > + err = as3722_gpio_direction_output(2, 1); > > + if (err < 0) { > > + error("as3722: failed to set GPIO#2 high: %d\n", err); > > + return err; > > + } > [...] > > On my board, this call results in UART corruption, like this: > > tegra-pcie: non-prefetchable memory: 0x13000000-0x20000000 > tegra-pcie: prefetchable memory: 0x20000000-0x40000000 > ??????b????b2x1, 1x1 configuration > ??5R?tegra-pcie: probing port 1, using 1 lanes > > Likely because GPIO#2 controls the +3.3V_LP0 rail, which powers the UART > level shifters. Commenting the function call out fixes the corruption and > PCI-E still works fine. If I add a udelay(500) after the above I'm not able to reproduce the UART breakage anymore. But I guess making the AS3722 GPIO code smarter would be helpful. In the kernel this is done by checking the invert bit and then setting the value accordingly. I suppose the same could be done for the mode bits. I'll see if I can work up a patch. Thierry -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 819 bytes Desc: not available URL: