[U-Boot] [PATCH v3 1/3] mx6: imx-regs: Provide a structure for GPC registers

[U-Boot] [PATCH v3 1/3] mx6: imx-regs: Provide a structure for GPC registers

[Fabio Estevam]

Introduce a structure for accessing the General Power Controller block (GPC)
registers.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v2:
- None
Changes since v1:
- None

 arch/arm/include/asm/arch-mx6/imx-regs.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 2631beb..22614fc 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -419,6 +419,19 @@ struct iomuxc {
 	u32 gpr[14];
 };
 
+struct gpc {
+	u32	cntr;
+	u32	pgr;
+	u32	imr1;
+	u32	imr2;
+	u32	imr3;
+	u32	imr4;
+	u32	isr1;
+	u32	isr2;
+	u32	isr3;
+	u32	isr4;
+};
+
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET		20
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET		16
-- 
1.9.1

[U-Boot] [PATCH v3 2/3] pcie_imx: Add mx6solox support

[Fabio Estevam]

Let PCI on mx6solox also be supported.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v2:
- Configure lvds1_clk_sel in run-time
Changes since v1:
- Put the definition of gpc inside CONFIG_MX6SX ifdef
- Use setbits_le32 to configure register CNTR
- Improve comments in the code
 arch/arm/cpu/armv7/mx6/clock.c        | 17 +++++++++++----
 arch/arm/include/asm/arch-mx6/iomux.h |  9 ++++++++
 drivers/pci/pcie_imx.c                | 40 +++++++++++++++++++++++++++++++----
 3 files changed, 58 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 820b8d5..18608de 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -509,6 +509,7 @@ int enable_pcie_clock(void)
 	struct anatop_regs *anatop_regs =
 		(struct anatop_regs *)ANATOP_BASE_ADDR;
 	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 lvds1_clk_sel;
 
 	/*
 	 * Here be dragons!
@@ -518,17 +519,25 @@ int enable_pcie_clock(void)
 	 * marked as ANATOP_MISC1 is actually documented in the PMU section
 	 * of the datasheet as PMU_MISC1.
 	 *
-	 * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
-	 * enable clock OUTPUT. This is important for PCI express link that
-	 * is clocked from the i.MX6.
+	 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
+	 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
+	 * for PCI express link that is clocked from the i.MX6.
 	 */
 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN		(1 << 12)
 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN		(1 << 10)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK	0x0000001F
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF	0xa
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF	0xb
+
+	if (is_cpu_type(MXC_CPU_MX6SX))
+		lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
+	else
+		lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
+
 	clrsetbits_le32(&anatop_regs->ana_misc1,
 			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
-			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
+			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 
 	/* PCIe reference clock sourced from AXI. */
 	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index f54db69..9b3a91f 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -19,6 +19,12 @@
 #define IOMUXC_GPR1_TEST_POWERDOWN		(1 << 18)
 
 /*
+ * IOMUXC_GPR5 bit fields
+ */
+#define IOMUXC_GPR5_PCIE_BTNRST			(1 << 19)
+#define IOMUXC_GPR5_PCIE_PERST			(1 << 18)
+
+/*
  * IOMUXC_GPR8 bit fields
  */
 #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK		(0x3f << 0)
@@ -35,12 +41,15 @@
 /*
  * IOMUXC_GPR12 bit fields
  */
+#define IOMUXC_GPR12_RX_EQ_2			(0x2 << 0)
+#define IOMUXC_GPR12_RX_EQ_MASK			(0x7 << 0)
 #define IOMUXC_GPR12_LOS_LEVEL_9		(0x9 << 4)
 #define IOMUXC_GPR12_LOS_LEVEL_MASK		(0x1f << 4)
 #define IOMUXC_GPR12_APPS_LTSSM_ENABLE		(1 << 10)
 #define IOMUXC_GPR12_DEVICE_TYPE_EP		(0x0 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_RC		(0x4 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_MASK		(0xf << 12)
+#define IOMUXC_GPR12_TEST_POWERDOWN		(1 << 30)
 
 /*
  * IOMUXC_GPR13 bit fields
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index a3982c4..fd7e4d4 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -23,13 +23,20 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
+#ifdef CONFIG_MX6SX
+#define MX6_DBI_ADDR	0x08ffc000
+#define MX6_IO_ADDR	0x08000000
+#define MX6_MEM_ADDR	0x08100000
+#define MX6_ROOT_ADDR	0x08f00000
+#else
 #define MX6_DBI_ADDR	0x01ffc000
-#define MX6_DBI_SIZE	0x4000
 #define MX6_IO_ADDR	0x01000000
-#define MX6_IO_SIZE	0x100000
 #define MX6_MEM_ADDR	0x01100000
-#define MX6_MEM_SIZE	0xe00000
 #define MX6_ROOT_ADDR	0x01f00000
+#endif
+#define MX6_DBI_SIZE	0x4000
+#define MX6_IO_SIZE	0x100000
+#define MX6_MEM_SIZE	0xe00000
 #define MX6_ROOT_SIZE	0xfc000
 
 /* PCIe Port Logic registers (memory-mapped) */
@@ -57,6 +64,8 @@
 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
 
+#define PCIE_PHY_PUP_REQ		(1 << 7)
+
 /* iATU registers */
 #define PCIE_ATU_VIEWPORT		0x900
 #define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
@@ -421,9 +430,19 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 static int imx6_pcie_assert_core_reset(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
+#if defined(CONFIG_MX6SX)
+	struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
+
+	/* SSP_EN is not used on MX6SX anymore */
+	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+	/* Force PCIe PHY reset */
+	setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+	/* Power up PCIe PHY */
+	setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+#else
 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
 	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
 
 	return 0;
 }
@@ -441,6 +460,12 @@ static int imx6_pcie_init_phy(void)
 			IOMUXC_GPR12_LOS_LEVEL_MASK,
 			IOMUXC_GPR12_LOS_LEVEL_9);
 
+#ifdef CONFIG_MX6SX
+	clrsetbits_le32(&iomuxc_regs->gpr[12],
+			IOMUXC_GPR12_RX_EQ_MASK,
+			IOMUXC_GPR12_RX_EQ_2);
+#endif
+
 	writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
 	       (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
 	       (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
@@ -517,9 +542,16 @@ static int imx6_pcie_deassert_core_reset(void)
 	 */
 	mdelay(50);
 
+#if defined(CONFIG_MX6SX)
+	/* SSP_EN is not used on MX6SX anymore */
+	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+	/* Clear PCIe PHY reset bit */
+	clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+#else
 	/* Enable PCIe */
 	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
 
 	imx6_pcie_toggle_reset();
 
-- 
1.9.1

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Fabio Estevam]

Tested with an Intel Wireless PCI 7260HMW card:

U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)                
                                                                                
CPU:   Freescale i.MX6SX rev1.0 at 792 MHz                                      
Reset cause: WDOG                                                               
Board: MX6SX SABRE SDB                                                          
I2C:   ready                                                                    
DRAM:  1 GiB                                                                    
MMC:   FSL_SDHC: 0                                                              
  00:01.0     - 16c3:abcd - Bridge device                                       
   01:00.0    - 8086:08b1 - Network controller                                  

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v2:
- None
Changes since v1:
- None
 include/configs/mx6sxsabresd.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 1eda65e..b92d944 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -198,6 +198,16 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(2, 1)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(2, 0)
+#endif
+
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
-- 
1.9.1

[U-Boot] [PATCH v3 2/3] pcie_imx: Add mx6solox support

[Marek Vasut]

On Monday, August 25, 2014 at 07:26:45 PM, Fabio Estevam wrote:
> Let PCI on mx6solox also be supported.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v2:
> - Configure lvds1_clk_sel in run-time
> Changes since v1:
> - Put the definition of gpc inside CONFIG_MX6SX ifdef
> - Use setbits_le32 to configure register CNTR
> - Improve comments in the code
>  arch/arm/cpu/armv7/mx6/clock.c        | 17 +++++++++++----
>  arch/arm/include/asm/arch-mx6/iomux.h |  9 ++++++++
>  drivers/pci/pcie_imx.c                | 40
> +++++++++++++++++++++++++++++++---- 3 files changed, 58 insertions(+), 8
> deletions(-)
> 

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Marek Vasut]

On Monday, August 25, 2014 at 07:26:46 PM, Fabio Estevam wrote:
> Tested with an Intel Wireless PCI 7260HMW card:
> 
> U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
> 
> CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
> Reset cause: WDOG
> Board: MX6SX SABRE SDB
> I2C:   ready
> DRAM:  1 GiB
> MMC:   FSL_SDHC: 0
>   00:01.0     - 16c3:abcd - Bridge device
>    01:00.0    - 8086:08b1 - Network controller
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Should this output be really part of the commit message?

Best regards,
Marek Vasut

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Fabio Estevam]

On Mon, Aug 25, 2014 at 4:50 PM, Marek Vasut <marex@denx.de> wrote:
> On Monday, August 25, 2014 at 07:26:46 PM, Fabio Estevam wrote:
>> Tested with an Intel Wireless PCI 7260HMW card:
>>
>> U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
>>
>> CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
>> Reset cause: WDOG
>> Board: MX6SX SABRE SDB
>> I2C:   ready
>> DRAM:  1 GiB
>> MMC:   FSL_SDHC: 0
>>   00:01.0     - 16c3:abcd - Bridge device
>>    01:00.0    - 8086:08b1 - Network controller
>>
>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
>
> Should this output be really part of the commit message?

Personally I don't see any problem with it, but if Stefano prefers I
can remove it and send a v4.

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Otavio Salvador]

On Mon, Aug 25, 2014 at 5:11 PM, Fabio Estevam <festevam@gmail.com> wrote:
> On Mon, Aug 25, 2014 at 4:50 PM, Marek Vasut <marex@denx.de> wrote:
>> On Monday, August 25, 2014 at 07:26:46 PM, Fabio Estevam wrote:
>>> Tested with an Intel Wireless PCI 7260HMW card:
>>>
>>> U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
>>>
>>> CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
>>> Reset cause: WDOG
>>> Board: MX6SX SABRE SDB
>>> I2C:   ready
>>> DRAM:  1 GiB
>>> MMC:   FSL_SDHC: 0
>>>   00:01.0     - 16c3:abcd - Bridge device
>>>    01:00.0    - 8086:08b1 - Network controller
>>>
>>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
>>
>> Should this output be really part of the commit message?
>
> Personally I don't see any problem with it, but if Stefano prefers I
> can remove it and send a v4.

I like to have it  included.

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Marek Vasut]

On Monday, August 25, 2014 at 10:24:19 PM, Otavio Salvador wrote:
> On Mon, Aug 25, 2014 at 5:11 PM, Fabio Estevam <festevam@gmail.com> wrote:
> > On Mon, Aug 25, 2014 at 4:50 PM, Marek Vasut <marex@denx.de> wrote:
> >> On Monday, August 25, 2014 at 07:26:46 PM, Fabio Estevam wrote:
> >>> Tested with an Intel Wireless PCI 7260HMW card:
> >>> 
> >>> U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
> >>> 
> >>> CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
> >>> Reset cause: WDOG
> >>> Board: MX6SX SABRE SDB
> >>> I2C:   ready
> >>> DRAM:  1 GiB
> >>> MMC:   FSL_SDHC: 0
> >>> 
> >>>   00:01.0     - 16c3:abcd - Bridge device
> >>>   
> >>>    01:00.0    - 8086:08b1 - Network controller
> >>> 
> >>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> >> 
> >> Should this output be really part of the commit message?
> > 
> > Personally I don't see any problem with it, but if Stefano prefers I
> > can remove it and send a v4.
> 
> I like to have it  included.

Please explain what exactly is the worth of having 50% of commit message contain 
standard U-Boot boot output, which is completely unrelated to what the commit 
implements. The rest of the commit message fails to explain what the commit 
does.

I would like to hear your reasoning for your claim.

Best regards,
Marek Vasut

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Otavio Salvador]

On Mon, Aug 25, 2014 at 5:28 PM, Marek Vasut <marex@denx.de> wrote:
> On Monday, August 25, 2014 at 10:24:19 PM, Otavio Salvador wrote:
>> On Mon, Aug 25, 2014 at 5:11 PM, Fabio Estevam <festevam@gmail.com> wrote:
>> > On Mon, Aug 25, 2014 at 4:50 PM, Marek Vasut <marex@denx.de> wrote:
>> >> On Monday, August 25, 2014 at 07:26:46 PM, Fabio Estevam wrote:
>> >>> Tested with an Intel Wireless PCI 7260HMW card:
>> >>>
>> >>> U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
>> >>>
>> >>> CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
>> >>> Reset cause: WDOG
>> >>> Board: MX6SX SABRE SDB
>> >>> I2C:   ready
>> >>> DRAM:  1 GiB
>> >>> MMC:   FSL_SDHC: 0
>> >>>
>> >>>   00:01.0     - 16c3:abcd - Bridge device
>> >>>
>> >>>    01:00.0    - 8086:08b1 - Network controller
>> >>>
>> >>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
>> >>
>> >> Should this output be really part of the commit message?
>> >
>> > Personally I don't see any problem with it, but if Stefano prefers I
>> > can remove it and send a v4.
>>
>> I like to have it  included.
>
> Please explain what exactly is the worth of having 50% of commit message contain
> standard U-Boot boot output, which is completely unrelated to what the commit
> implements. The rest of the commit message fails to explain what the commit
> does.
>
> I would like to hear your reasoning for your claim.

I don't have to explain. I like it there and I think it adds an
information which I feel it is valid. You said you does not like it so
please explain your reasoning ;-)

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Marek Vasut]

On Monday, August 25, 2014 at 10:31:18 PM, Otavio Salvador wrote:
> On Mon, Aug 25, 2014 at 5:28 PM, Marek Vasut <marex@denx.de> wrote:
> > On Monday, August 25, 2014 at 10:24:19 PM, Otavio Salvador wrote:
> >> On Mon, Aug 25, 2014 at 5:11 PM, Fabio Estevam <festevam@gmail.com> wrote:
> >> > On Mon, Aug 25, 2014 at 4:50 PM, Marek Vasut <marex@denx.de> wrote:
> >> >> On Monday, August 25, 2014 at 07:26:46 PM, Fabio Estevam wrote:
> >> >>> Tested with an Intel Wireless PCI 7260HMW card:
> >> >>> 
> >> >>> U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
> >> >>> 
> >> >>> CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
> >> >>> Reset cause: WDOG
> >> >>> Board: MX6SX SABRE SDB
> >> >>> I2C:   ready
> >> >>> DRAM:  1 GiB
> >> >>> MMC:   FSL_SDHC: 0
> >> >>> 
> >> >>>   00:01.0     - 16c3:abcd - Bridge device
> >> >>>   
> >> >>>    01:00.0    - 8086:08b1 - Network controller
> >> >>> 
> >> >>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> >> >> 
> >> >> Should this output be really part of the commit message?
> >> > 
> >> > Personally I don't see any problem with it, but if Stefano prefers I
> >> > can remove it and send a v4.
> >> 
> >> I like to have it  included.
> > 
> > Please explain what exactly is the worth of having 50% of commit message
> > contain standard U-Boot boot output, which is completely unrelated to
> > what the commit implements. The rest of the commit message fails to
> > explain what the commit does.
> > 
> > I would like to hear your reasoning for your claim.
> 
> I don't have to explain.

Sorry, but this is in no way how you proceed with a constructive discussion. I 
will cut the discussion here, since I am starting to see a recurring pattern and 
I am growing tired of this.

[...]

Best regards,
Marek Vasut

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Fabio Estevam]

Hi Stefano,

On Mon, Aug 25, 2014 at 5:11 PM, Fabio Estevam <festevam@gmail.com> wrote:
> On Mon, Aug 25, 2014 at 4:50 PM, Marek Vasut <marex@denx.de> wrote:
>> On Monday, August 25, 2014 at 07:26:46 PM, Fabio Estevam wrote:
>>> Tested with an Intel Wireless PCI 7260HMW card:
>>>
>>> U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
>>>
>>> CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
>>> Reset cause: WDOG
>>> Board: MX6SX SABRE SDB
>>> I2C:   ready
>>> DRAM:  1 GiB
>>> MMC:   FSL_SDHC: 0
>>>   00:01.0     - 16c3:abcd - Bridge device
>>>    01:00.0    - 8086:08b1 - Network controller
>>>
>>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
>>
>> Should this output be really part of the commit message?
>
> Personally I don't see any problem with it, but if Stefano prefers I
> can remove it and send a v4.

Please let me know if you want me to resend this series or if you are
fine with it.

Thanks

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Marek Vasut]

On Friday, August 29, 2014 at 10:19:11 PM, Fabio Estevam wrote:
> Hi Stefano,
> 
> On Mon, Aug 25, 2014 at 5:11 PM, Fabio Estevam <festevam@gmail.com> wrote:
> > On Mon, Aug 25, 2014 at 4:50 PM, Marek Vasut <marex@denx.de> wrote:
> >> On Monday, August 25, 2014 at 07:26:46 PM, Fabio Estevam wrote:
> >>> Tested with an Intel Wireless PCI 7260HMW card:
> >>> 
> >>> U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
> >>> 
> >>> CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
> >>> Reset cause: WDOG
> >>> Board: MX6SX SABRE SDB
> >>> I2C:   ready
> >>> DRAM:  1 GiB
> >>> MMC:   FSL_SDHC: 0
> >>> 
> >>>   00:01.0     - 16c3:abcd - Bridge device
> >>>   
> >>>    01:00.0    - 8086:08b1 - Network controller
> >>> 
> >>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> >> 
> >> Should this output be really part of the commit message?
> > 
> > Personally I don't see any problem with it, but if Stefano prefers I
> > can remove it and send a v4.
> 
> Please let me know if you want me to resend this series or if you are
> fine with it.

A proper commit message describing the change would be very useful. Thank you!

Best regards,
Marek Vasut

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Fabio Estevam]

On Fri, Aug 29, 2014 at 7:29 PM, Marek Vasut <marex@denx.de> wrote:

> A proper commit message describing the change would be very useful. Thank you!

Sorry, but I don't understand your suggestion.

The Subject says that I am adding PCI support to the mx6sxsabresd board.

Then I say that I tested it with a PCI card and put the log showing
that the card was detected.

I really don't know how I can be clearer in the description of this
simple patch.

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Marek Vasut]

On Saturday, August 30, 2014 at 12:54:27 AM, Fabio Estevam wrote:
> On Fri, Aug 29, 2014 at 7:29 PM, Marek Vasut <marex@denx.de> wrote:
> > A proper commit message describing the change would be very useful. Thank
> > you!
> 
> Sorry, but I don't understand your suggestion.
> 
> The Subject says that I am adding PCI support to the mx6sxsabresd board.
> 
> Then I say that I tested it with a PCI card and put the log showing
> that the card was detected.
> 
> I really don't know how I can be clearer in the description of this
> simple patch.

Just one or two lines explaining that you're adding the sabre-sx PCIe support in 
the commit message would do, really.

Best regards,
Marek Vasut

[U-Boot] [PATCH v3 1/3] mx6: imx-regs: Provide a structure for GPC registers

[Stefano Babic]

On 25/08/2014 19:26, Fabio Estevam wrote:
> Introduce a structure for accessing the General Power Controller block (GPC)
> registers.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v3 2/3] pcie_imx: Add mx6solox support

[Stefano Babic]

On 25/08/2014 19:26, Fabio Estevam wrote:
> Let PCI on mx6solox also be supported.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic



-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v3 3/3] mx6sxsabresd: Add PCI support

[Stefano Babic]

On 25/08/2014 19:26, Fabio Estevam wrote:
> Tested with an Intel Wireless PCI 7260HMW card:
> 
> U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)                
>                                                                                 
> CPU:   Freescale i.MX6SX rev1.0 at 792 MHz                                      
> Reset cause: WDOG                                                               
> Board: MX6SX SABRE SDB                                                          
> I2C:   ready                                                                    
> DRAM:  1 GiB                                                                    
> MMC:   FSL_SDHC: 0                                                              
>   00:01.0     - 16c3:abcd - Bridge device                                       
>    01:00.0    - 8086:08b1 - Network controller                                  
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

I have no problem with the commit message.

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================