[U-Boot] [WIP PATCH 4/4 v2] arm: socfpga: Don't enable dcache (because of cadence SPI driver problem)

[Marek Vasut <marex@denx.de>]

On Tuesday, September 23, 2014 at 04:08:32 PM, Stefan Roese wrote:
> The Cadence SPI driver currently has some problems when the dcache is
> enabled. As a work-around until this problem is fixed in the SPI driver,
> lets not enable the dcache on the socfpga platforms. As its also done in
> the rocketboards version.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> ---
>  board/altera/socfpga/socfpga_cyclone5.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/board/altera/socfpga/socfpga_cyclone5.c
> b/board/altera/socfpga/socfpga_cyclone5.c index 10f15e0..3f19d89 100644
> --- a/board/altera/socfpga/socfpga_cyclone5.c
> +++ b/board/altera/socfpga/socfpga_cyclone5.c
> @@ -76,7 +76,9 @@ int board_phy_config(struct phy_device *phydev)
>  int board_init(void)
>  {
>  	icache_enable();
> +#if 0 // test-only: disable dcache for now as it causes problems with the
> SPI driver dcache_enable();
> +#endif

This means the DMA code in cadence driver is not flushing/invalidating cache
as it should. Are you planning to fix it proper eventually?

But this is really a good thing that you found this out! That's an important 
information, thanks!

Best regards,
Marek Vasut