From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Thu, 25 Sep 2014 17:25:55 +0200 Subject: [U-Boot] [WIP PATCH 0/2 v2] arm: socfpga: Add Cadence QSPI support In-Reply-To: <1411481312-9929-1-git-send-email-sr@denx.de> References: <1411481312-9929-1-git-send-email-sr@denx.de> Message-ID: <201409251725.55566.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tuesday, September 23, 2014 at 04:08:28 PM, Stefan Roese wrote: > Hi SoCFPGA-developers! > > So this is my 2nd posting regarding the Candence SPI driver on SoCFPGA. > I got it working now. But only with one quick-hack, as you can see in > patch 4/4. Which disabled the dcache. Or more precise, doesn't enable it. > Thanks to Michael who pointed this out. > > Since I really can't spend more time on this in this week, and > Chin Liang mentioned that he might be able to help out (thanks > again for this), I'm posting this version now for all others > as a reference. Hopefully Chin Liang (or some other volunteer) can fix > this cache issue in a generic way. I will keep tracking this in my repository so it doesn't get lost. I am not sure I will get to fixing it though. Best regards, Marek Vasut