[U-Boot] [PATCH 4/7] spi: altera: Zap endless loop

Marek Vasut
2014-10-19T18:43:36Z

The driver contained an endless loop when waiting for TX completion,
this is a bad idea since if the hardware fails, the loop might spin
forever. Add timeout and handle it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
---
drivers/spi/altera_spi.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index 373ce30..ee65ec2 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -129,6 +129,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
uint bytes = bitlen / 8;
const uchar *txp = dout;
uchar *rxp = din;
+ int timeout = 10000;
+ uint32_t reg;

debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
slave->bus, slave->cs, bitlen, bytes, flags);
@@ -154,8 +156,16 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
debug("%s: tx:%x ", __func__, d);
writel(d, &altspi->regs->txdata);

- while (!(readl(&altspi->regs->status) & ALTERA_SPI_STATUS_RRDY_MSK))
- ;
+ while (--timeout) {
+ reg = readl(&altspi->regs->status);
+ if (reg & ALTERA_SPI_STATUS_RRDY_MSK)
+ break;
+ }
+
+ if (!timeout) {
+ printf("%s: Transmission timed out!\n", __func__);
+ goto done;
+ }

d = readl(&altspi->regs->rxdata);
if (rxp)
--
2.1.1