[U-Boot] [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms

[U-Boot] [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms

[Yuantian.Tang at freescale.com]

From: Tang Yuantian <Yuantian.Tang@freescale.com>

These patches depend on the following patches:
https://patchwork.ozlabs.org/patch/389949/
https://patchwork.ozlabs.org/patch/389950/
https://patchwork.ozlabs.org/patch/389951/
https://patchwork.ozlabs.org/patch/389952/

Tang Yuantian (4):
  Add deep sleep framework support for Freescale QorIQ platforms
  ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation
  arm: ls102xa: Fixed a register definition error
  arm: ls1021qds: Add deep sleep support

 arch/arm/cpu/armv7/virt-v7.c                      | 14 +++---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
 board/freescale/ls1021aqds/ddr.c                  |  7 +++
 board/freescale/ls1021aqds/ls1021aqds.c           | 60 +++++++++++++++++++++++
 common/board_f.c                                  | 10 ++++
 drivers/ddr/fsl/arm_ddr_gen3.c                    | 48 ++++++++++++++++--
 include/configs/ls1021aqds.h                      |  4 ++
 include/fsl_ddr_sdram.h                           |  2 +
 include/fsl_sleep.h                               | 32 ++++++++++++
 9 files changed, 167 insertions(+), 12 deletions(-)
 create mode 100644 include/fsl_sleep.h

-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Yuantian.Tang at freescale.com]

From: Tang Yuantian <Yuantian.Tang@freescale.com>

When Freescale QorIQ SoCs wake up from deep sleep, control is
passed to the primary core that starts executing uboot. After
re-initialized some IP blocks, like DDRC, kernel will take
responsibility to continue to restore environment it leaves before.

This patch adds the deep sleep framework support for all Freescale
QorIQ platforms that use generic_board configuation.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
 common/board_f.c               | 10 +++++++++
 drivers/ddr/fsl/arm_ddr_gen3.c | 48 +++++++++++++++++++++++++++++++++++++-----
 include/fsl_ddr_sdram.h        |  2 ++
 include/fsl_sleep.h            | 32 ++++++++++++++++++++++++++++
 4 files changed, 87 insertions(+), 5 deletions(-)
 create mode 100644 include/fsl_sleep.h

diff --git a/common/board_f.c b/common/board_f.c
index e6aa298..b736d29 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -56,6 +56,9 @@
 #endif
 #include <dm/root.h>
 #include <linux/compiler.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
 
 /*
  * Pointer to initial global data area
@@ -921,6 +924,9 @@ static init_fnc_t init_sequence_f[] = {
 #if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
 	init_func_ram,
 #endif
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	fsl_dp_resume,
+#endif
 #ifdef CONFIG_POST
 	post_init_f,
 #endif
@@ -1027,6 +1033,10 @@ void board_init_f(ulong boot_flags)
 	gd->flags = boot_flags;
 	gd->have_console = 0;
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	if (is_warm_boot())
+		gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#endif
 	if (initcall_run_list(init_sequence_f))
 		hang();
 
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 59f2fd6..1a9d82b 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -12,6 +12,9 @@
 #include <asm/processor.h>
 #include <fsl_immap.h>
 #include <fsl_ddr.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -92,7 +95,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 	ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 	ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-	ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 	ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 	ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 	ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
@@ -105,8 +107,25 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 	ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 	ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-	ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
-	ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	if (is_warm_boot()) {
+		ddr_out32(&ddr->sdram_cfg_2,
+			  regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+		ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+		ddr_out32(&ddr->init_ext_addr, (1 << 31));
+
+		/* DRAM VRef will not be trained */
+		temp_sdram_cfg = ddr_in32(&ddr->ddr_cdr2);
+		temp_sdram_cfg &= ~DDR_CDR2_VREF_TRAIN_EN;
+		ddr_out32(&ddr->ddr_cdr2, temp_sdram_cfg);
+	} else
+#endif
+	{
+		ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+		ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
+		ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+		ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+	}
 
 	ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 	ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
@@ -128,7 +147,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 	ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 	ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
-	ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 	ddr_out32(&ddr->err_disable, regs->err_disable);
 	ddr_out32(&ddr->err_int_en, regs->err_int_en);
 	for (i = 0; i < 32; i++) {
@@ -167,8 +185,20 @@ step2:
 	udelay(500);
 	asm volatile("dsb sy;isb");
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* enter self-refresh */
+		temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+		ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+		/* do board specific memory setup */
+		fsl_dp_mem_setup();
+
+		temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
+	} else
+#endif
+		temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
 	/* Let the controller go */
-	temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 	ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 	asm volatile("dsb sy;isb");
 
@@ -211,4 +241,12 @@ step2:
 
 	if (timeout <= 0)
 		printf("Waiting for D_INIT timeout. Memory may not work.\n");
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* exit self-refresh */
+		temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+		ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+	}
+#endif
 }
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 5b03c14..b69b1dc 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -114,6 +114,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define SDRAM_CFG_2T_EN			0x00008000
 #define SDRAM_CFG_BI			0x00000001
 
+#define SDRAM_CFG2_FRC_SR		0x80000000
 #define SDRAM_CFG2_D_INIT		0x00000010
 #define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
 #define SDRAM_CFG2_ODT_NEVER		0
@@ -163,6 +164,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
 #define DDR_CDR2_VREF_OVRD(x)	(0x00008080 | ((((x) - 37) & 0x3F) << 8))
+#define DDR_CDR2_VREF_TRAIN_EN	0x00000080
 
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
 	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
diff --git a/include/fsl_sleep.h b/include/fsl_sleep.h
new file mode 100644
index 0000000..429e302
--- /dev/null
+++ b/include/fsl_sleep.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DEEP_SLEEP_H
+#define __DEEP_SLEEP_H
+
+/*
+ * Functions prototype for sleep.
+ * Each platform that supports deep sleep needs to
+ * implement them on their own.
+ */
+
+/* determine if it is a wakeup from deep sleep */
+bool is_warm_boot(void);
+
+/* board specific memory setup, like CKE isolation */
+void fsl_dp_mem_setup(void);
+
+/* clean up everything and jump to kernel */
+int fsl_dp_resume(void);
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+void fsl_dp_ddr_restore(void);
+
+#endif
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 2/4] ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation

[Yuantian.Tang at freescale.com]

From: Tang Yuantian <Yuantian.Tang@freescale.com>

Defining variable gic_dist_addr as a globe one prevents function
armv7_init_nonsec() from being used before relocation which is
the case in the deep sleep resume process on Freescale QorIQ SoC
platforms.
This patch removes this limitation by adding a extra same meaning
local variable. In this way, no exsiting codes get corrupts.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
 arch/arm/cpu/armv7/virt-v7.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 651ca40..e1dfce9 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -75,6 +75,7 @@ int armv7_init_nonsec(void)
 {
 	unsigned int reg;
 	unsigned itlinesnr, i;
+	unsigned long gic_base_addr;
 
 	/* check whether the CPU supports the security extensions */
 	reg = read_id_pfr1();
@@ -89,23 +90,24 @@ int armv7_init_nonsec(void)
 	 * any access to it will trap.
 	 */
 
-	gic_dist_addr = get_gicd_base_address();
-	if (gic_dist_addr == -1)
+	gic_base_addr = get_gicd_base_address();
+	gic_dist_addr = gic_base_addr;
+	if (gic_base_addr == -1)
 		return -1;
 
 	/* enable the GIC distributor */
-	writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
-	       gic_dist_addr + GICD_CTLR);
+	writel(readl(gic_base_addr + GICD_CTLR) | 0x03,
+	       gic_base_addr + GICD_CTLR);
 
 	/* TYPER[4:0] contains an encoded number of available interrupts */
-	itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
+	itlinesnr = readl(gic_base_addr + GICD_TYPER) & 0x1f;
 
 	/* set all bits in the GIC group registers to one to allow access
 	 * from non-secure state. The first 32 interrupts are private per
 	 * CPU and will be set later when enabling the GIC for each core
 	 */
 	for (i = 1; i <= itlinesnr; i++)
-		writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
+		writel((unsigned)-1, gic_base_addr + GICD_IGROUPRn + 4 * i);
 
 #ifndef CONFIG_ARMV7_PSCI
 	smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 3/4] arm: ls102xa: Fixed a register definition error

[Yuantian.Tang at freescale.com]

From: Tang Yuantian <Yuantian.Tang@freescale.com>

There are 8 SCFG_SPARECR registers in SCFG memory block, not one.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..b5db720 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,7 +182,7 @@ struct ccsr_scfg {
 	u32 etsecmcr;
 	u32 sdhciovserlcr;
 	u32 resv14[61];
-	u32 sparecr;
+	u32 sparecr[8];
 };
 
 /* Clocking */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 4/4] arm: ls1021qds: Add deep sleep support

[Yuantian.Tang at freescale.com]

From: Tang Yuantian <Yuantian.Tang@freescale.com>

Add deep sleep support on Freescale LS1021QDS platform.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
 board/freescale/ls1021aqds/ddr.c        |  7 ++++
 board/freescale/ls1021aqds/ls1021aqds.c | 60 +++++++++++++++++++++++++++++++++
 include/configs/ls1021aqds.h            |  4 +++
 3 files changed, 71 insertions(+)

diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 5898e33..6dad4cc 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -8,6 +8,9 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include "ddr.h"
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -156,6 +159,10 @@ phys_size_t initdram(int board_type)
 	puts("Initializing DDR....using SPD\n");
 	dram_size = fsl_ddr_sdram();
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	fsl_dp_ddr_restore();
+#endif
+
 	return dram_size;
 }
 
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 12e83f7..e9dce36 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -253,3 +253,63 @@ u16 flash_read16(void *addr)
 
 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 }
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+/* determine if it is a warm boot */
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+		return 1;
+
+	return 0;
+}
+
+void fsl_dp_mem_setup(void)
+{
+	/* does not provide HW signals for power management */
+	QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
+	udelay(1);
+}
+
+void fsl_dp_ddr_restore(void)
+{
+#define DDR_BUFF_LEN	128
+	u64 *src, *dst;
+	int i;
+	struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+	if (!is_warm_boot())
+		return;
+
+	/* get the address of ddr date from SPARECR3, little endian */
+	src = (u64 *)in_le32(&scfg->sparecr[2]);
+	dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+	for (i = 0; i < DDR_BUFF_LEN / 8; i++)
+		*dst++ = *src++;
+}
+
+int fsl_dp_resume(void)
+{
+	u32 start_addr;
+	void (*kernel_resume)(void);
+	struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+	if (!is_warm_boot())
+		return 0;
+
+	enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+	armv7_init_nonsec();
+	cleanup_before_linux();
+
+	/* Get the entry address and jump to kernel */
+	start_addr = in_le32(&scfg->sparecr[1]);
+	debug("Entry address is 0x%08x\n", start_addr);
+	kernel_resume = (void (*)(void))start_addr;
+	secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
+
+	return 0;
+}
+#endif
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index bb47813..448a07e 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -19,6 +19,10 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 
+#define CONFIG_FSL_DEEP_SLEEP
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+#endif
 /*
  * Size of malloc() pool
  */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Yuantian.Tang at freescale.com]

From: Tang Yuantian <Yuantian.Tang@freescale.com>

When Freescale QorIQ SoCs wake up from deep sleep, control is
passed to the primary core that starts executing uboot. After
re-initialized some IP blocks, like DDRC, kernel will take
responsibility to continue to restore environment it leaves before.

This patch adds the deep sleep framework support for all Freescale
QorIQ platforms that use generic_board configuation.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
 common/board_f.c               | 10 +++++++++
 drivers/ddr/fsl/arm_ddr_gen3.c | 48 +++++++++++++++++++++++++++++++++++++-----
 include/fsl_ddr_sdram.h        |  2 ++
 include/fsl_sleep.h            | 32 ++++++++++++++++++++++++++++
 4 files changed, 87 insertions(+), 5 deletions(-)
 create mode 100644 include/fsl_sleep.h

diff --git a/common/board_f.c b/common/board_f.c
index e6aa298..b736d29 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -56,6 +56,9 @@
 #endif
 #include <dm/root.h>
 #include <linux/compiler.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
 
 /*
  * Pointer to initial global data area
@@ -921,6 +924,9 @@ static init_fnc_t init_sequence_f[] = {
 #if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
 	init_func_ram,
 #endif
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	fsl_dp_resume,
+#endif
 #ifdef CONFIG_POST
 	post_init_f,
 #endif
@@ -1027,6 +1033,10 @@ void board_init_f(ulong boot_flags)
 	gd->flags = boot_flags;
 	gd->have_console = 0;
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	if (is_warm_boot())
+		gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#endif
 	if (initcall_run_list(init_sequence_f))
 		hang();
 
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 59f2fd6..1a9d82b 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -12,6 +12,9 @@
 #include <asm/processor.h>
 #include <fsl_immap.h>
 #include <fsl_ddr.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -92,7 +95,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 	ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 	ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-	ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 	ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 	ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 	ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
@@ -105,8 +107,25 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 	ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 	ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-	ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
-	ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	if (is_warm_boot()) {
+		ddr_out32(&ddr->sdram_cfg_2,
+			  regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+		ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+		ddr_out32(&ddr->init_ext_addr, (1 << 31));
+
+		/* DRAM VRef will not be trained */
+		temp_sdram_cfg = ddr_in32(&ddr->ddr_cdr2);
+		temp_sdram_cfg &= ~DDR_CDR2_VREF_TRAIN_EN;
+		ddr_out32(&ddr->ddr_cdr2, temp_sdram_cfg);
+	} else
+#endif
+	{
+		ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+		ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
+		ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+		ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+	}
 
 	ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 	ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
@@ -128,7 +147,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 	ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 	ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
-	ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 	ddr_out32(&ddr->err_disable, regs->err_disable);
 	ddr_out32(&ddr->err_int_en, regs->err_int_en);
 	for (i = 0; i < 32; i++) {
@@ -167,8 +185,20 @@ step2:
 	udelay(500);
 	asm volatile("dsb sy;isb");
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* enter self-refresh */
+		temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+		ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+		/* do board specific memory setup */
+		fsl_dp_mem_setup();
+
+		temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
+	} else
+#endif
+		temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
 	/* Let the controller go */
-	temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 	ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 	asm volatile("dsb sy;isb");
 
@@ -211,4 +241,12 @@ step2:
 
 	if (timeout <= 0)
 		printf("Waiting for D_INIT timeout. Memory may not work.\n");
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* exit self-refresh */
+		temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+		ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+	}
+#endif
 }
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 5b03c14..b69b1dc 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -114,6 +114,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define SDRAM_CFG_2T_EN			0x00008000
 #define SDRAM_CFG_BI			0x00000001
 
+#define SDRAM_CFG2_FRC_SR		0x80000000
 #define SDRAM_CFG2_D_INIT		0x00000010
 #define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
 #define SDRAM_CFG2_ODT_NEVER		0
@@ -163,6 +164,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
 #define DDR_CDR2_VREF_OVRD(x)	(0x00008080 | ((((x) - 37) & 0x3F) << 8))
+#define DDR_CDR2_VREF_TRAIN_EN	0x00000080
 
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
 	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
diff --git a/include/fsl_sleep.h b/include/fsl_sleep.h
new file mode 100644
index 0000000..429e302
--- /dev/null
+++ b/include/fsl_sleep.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DEEP_SLEEP_H
+#define __DEEP_SLEEP_H
+
+/*
+ * Functions prototype for sleep.
+ * Each platform that supports deep sleep needs to
+ * implement them on their own.
+ */
+
+/* determine if it is a wakeup from deep sleep */
+bool is_warm_boot(void);
+
+/* board specific memory setup, like CKE isolation */
+void fsl_dp_mem_setup(void);
+
+/* clean up everything and jump to kernel */
+int fsl_dp_resume(void);
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+void fsl_dp_ddr_restore(void);
+
+#endif
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Tom Rini]

On Sun, Sep 28, 2014 at 04:59:45PM +0800, Yuantian.Tang at freescale.com wrote:
> From: Tang Yuantian <Yuantian.Tang@freescale.com>
> 
> When Freescale QorIQ SoCs wake up from deep sleep, control is
> passed to the primary core that starts executing uboot. After
> re-initialized some IP blocks, like DDRC, kernel will take
> responsibility to continue to restore environment it leaves before.
> 
> This patch adds the deep sleep framework support for all Freescale
> QorIQ platforms that use generic_board configuation.
> 
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> ---
>  common/board_f.c               | 10 +++++++++
>  drivers/ddr/fsl/arm_ddr_gen3.c | 48 +++++++++++++++++++++++++++++++++++++-----
>  include/fsl_ddr_sdram.h        |  2 ++
>  include/fsl_sleep.h            | 32 ++++++++++++++++++++++++++++
>  4 files changed, 87 insertions(+), 5 deletions(-)
>  create mode 100644 include/fsl_sleep.h
> 
> diff --git a/common/board_f.c b/common/board_f.c
> index e6aa298..b736d29 100644
> --- a/common/board_f.c
> +++ b/common/board_f.c
> @@ -56,6 +56,9 @@
>  #endif
>  #include <dm/root.h>
>  #include <linux/compiler.h>
> +#ifdef CONFIG_FSL_DEEP_SLEEP
> +#include <fsl_sleep.h>
> +#endif
>  
>  /*
>   * Pointer to initial global data area
> @@ -921,6 +924,9 @@ static init_fnc_t init_sequence_f[] = {
>  #if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
>  	init_func_ram,
>  #endif
> +#ifdef CONFIG_FSL_DEEP_SLEEP
> +	fsl_dp_resume,
> +#endif

Is there not an existing hook you can use here instead?  Is misc_init_f
too early?  If we're going to add a new hook in here, it needs to be
somewhat generically named, with the requirements of the system spelled
out.  Some TI parts have a (setting aside marketing-speak) similar
function and I believe the U-Boot patches for that use an existing hook
to notice what happened and do what's needed.  Thanks!

-- 
Tom
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[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Yuantian Tang]

> -----Original Message-----
> From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Tom Rini
> Sent: Wednesday, October 22, 2014 9:54 PM
> To: Tang Yuantian-B29983
> Cc: albert.u.boot at aribaud.net; Jin Zhengxiong-R64188; u-boot at lists.denx.de;
> Sun York-R58495
> Subject: Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for
> Freescale QorIQ platforms
> 
> On Sun, Sep 28, 2014 at 04:59:45PM +0800, Yuantian.Tang at freescale.com
> wrote:
> > From: Tang Yuantian <Yuantian.Tang@freescale.com>
> >
> > When Freescale QorIQ SoCs wake up from deep sleep, control is passed
> > to the primary core that starts executing uboot. After re-initialized
> > some IP blocks, like DDRC, kernel will take responsibility to continue
> > to restore environment it leaves before.
> >
> > This patch adds the deep sleep framework support for all Freescale
> > QorIQ platforms that use generic_board configuation.
> >
> > Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> > ---
> >  common/board_f.c               | 10 +++++++++
> >  drivers/ddr/fsl/arm_ddr_gen3.c | 48
> +++++++++++++++++++++++++++++++++++++-----
> >  include/fsl_ddr_sdram.h        |  2 ++
> >  include/fsl_sleep.h            | 32 ++++++++++++++++++++++++++++
> >  4 files changed, 87 insertions(+), 5 deletions(-)  create mode 100644
> > include/fsl_sleep.h
> >
> > diff --git a/common/board_f.c b/common/board_f.c index
> > e6aa298..b736d29 100644
> > --- a/common/board_f.c
> > +++ b/common/board_f.c
> > @@ -56,6 +56,9 @@
> >  #endif
> >  #include <dm/root.h>
> >  #include <linux/compiler.h>
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +#include <fsl_sleep.h>
> > +#endif
> >
> >  /*
> >   * Pointer to initial global data area @@ -921,6 +924,9 @@ static
> > init_fnc_t init_sequence_f[] = {  #if defined(CONFIG_MIPS) ||
> > defined(CONFIG_PPC)
> >  	init_func_ram,
> >  #endif
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +	fsl_dp_resume,
> > +#endif
> 
> Is there not an existing hook you can use here instead?  Is misc_init_f too early?
Misc_init_f is too early, we need to put it between DDR initialization and relocation.

> If we're going to add a new hook in here, it needs to be somewhat generically
> named, with the requirements of the system spelled out.  
It is Freescale specific. Wouldn't be a misleading for other platforms that don't jump to kernel here?

> Some TI parts have a
> (setting aside marketing-speak) similar function and I believe the U-Boot patches
> for that use an existing hook to notice what happened and do what's needed.
Which function did you refer to? I can check if it can be used.

Thanks,
Yuantian

> Thanks!
> 

> --
> Tom

[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[York Sun]

Yuantian,

Tom didn't suggest a specific hook. If you can use existing one, you don't have to create a new one. It's preferred if you can find a good place in existing xxx_f functions.

York

-------- Original Message --------
From: Tang Yuantian-B29983
Sent: Wed, 22/10/2014 19:53
To: Tom Rini
CC: albert.u.boot at aribaud.net; Jin Zhengxiong-R64188 ; u-boot at lists.denx.de; Sun York-R58495
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms


> -----Original Message-----
> From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Tom Rini
> Sent: Wednesday, October 22, 2014 9:54 PM
> To: Tang Yuantian-B29983
> Cc: albert.u.boot at aribaud.net; Jin Zhengxiong-R64188; u-boot at lists.denx.de;
> Sun York-R58495
> Subject: Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for
> Freescale QorIQ platforms
>
> On Sun, Sep 28, 2014 at 04:59:45PM +0800, Yuantian.Tang at freescale.com
> wrote:
> > From: Tang Yuantian <Yuantian.Tang@freescale.com>
> >
> > When Freescale QorIQ SoCs wake up from deep sleep, control is passed
> > to the primary core that starts executing uboot. After re-initialized
> > some IP blocks, like DDRC, kernel will take responsibility to continue
> > to restore environment it leaves before.
> >
> > This patch adds the deep sleep framework support for all Freescale
> > QorIQ platforms that use generic_board configuation.
> >
> > Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> > ---
> >  common/board_f.c               | 10 +++++++++
> >  drivers/ddr/fsl/arm_ddr_gen3.c | 48
> +++++++++++++++++++++++++++++++++++++-----
> >  include/fsl_ddr_sdram.h        |  2 ++
> >  include/fsl_sleep.h            | 32 ++++++++++++++++++++++++++++
> >  4 files changed, 87 insertions(+), 5 deletions(-)  create mode 100644
> > include/fsl_sleep.h
> >
> > diff --git a/common/board_f.c b/common/board_f.c index
> > e6aa298..b736d29 100644
> > --- a/common/board_f.c
> > +++ b/common/board_f.c
> > @@ -56,6 +56,9 @@
> >  #endif
> >  #include <dm/root.h>
> >  #include <linux/compiler.h>
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +#include <fsl_sleep.h>
> > +#endif
> >
> >  /*
> >   * Pointer to initial global data area @@ -921,6 +924,9 @@ static
> > init_fnc_t init_sequence_f[] = {  #if defined(CONFIG_MIPS) ||
> > defined(CONFIG_PPC)
> >      init_func_ram,
> >  #endif
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +   fsl_dp_resume,
> > +#endif
>
> Is there not an existing hook you can use here instead?  Is misc_init_f too early?
Misc_init_f is too early, we need to put it between DDR initialization and relocation.

> If we're going to add a new hook in here, it needs to be somewhat generically
> named, with the requirements of the system spelled out.
It is Freescale specific. Wouldn't be a misleading for other platforms that don't jump to kernel here?

> Some TI parts have a
> (setting aside marketing-speak) similar function and I believe the U-Boot patches
> for that use an existing hook to notice what happened and do what's needed.
Which function did you refer to? I can check if it can be used.

Thanks,
Yuantian

> Thanks!
>

> --
> Tom

[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Yuantian Tang]

Thanks for your hint. Unfortunately I can't find such place.
It needs to be placed between DDR initialization and relocation.
It is used on both PPC and ARM platforms.
Do you have any sugguestions?

Thanks,
Yuantian

From: Sun York-R58495
Sent: Thursday, October 23, 2014 11:06 AM
To: Tang Yuantian-B29983; Tom Rini
Cc: albert.u.boot at aribaud.net; Jin Zhengxiong-R64188; u-boot at lists.denx.de
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms


Yuantian,

Tom didn't suggest a specific hook. If you can use existing one, you don't have to create a new one. It's preferred if you can find a good place in existing xxx_f functions.

York

-------- Original Message --------
From: Tang Yuantian-B29983
Sent: Wed, 22/10/2014 19:53
To: Tom Rini
CC: albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>; Jin Zhengxiong-R64188 ; u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>; Sun York-R58495
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

> -----Original Message-----
> From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Tom Rini
> Sent: Wednesday, October 22, 2014 9:54 PM
> To: Tang Yuantian-B29983
> Cc: albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>; Jin Zhengxiong-R64188; u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>;
> Sun York-R58495
> Subject: Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for
> Freescale QorIQ platforms
>
> On Sun, Sep 28, 2014 at 04:59:45PM +0800, Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>
> wrote:
> > From: Tang Yuantian <Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>>
> >
> > When Freescale QorIQ SoCs wake up from deep sleep, control is passed
> > to the primary core that starts executing uboot. After re-initialized
> > some IP blocks, like DDRC, kernel will take responsibility to continue
> > to restore environment it leaves before.
> >
> > This patch adds the deep sleep framework support for all Freescale
> > QorIQ platforms that use generic_board configuation.
> >
> > Signed-off-by: Tang Yuantian <Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>>
> > ---
> >  common/board_f.c               | 10 +++++++++
> >  drivers/ddr/fsl/arm_ddr_gen3.c | 48
> +++++++++++++++++++++++++++++++++++++-----
> >  include/fsl_ddr_sdram.h        |  2 ++
> >  include/fsl_sleep.h            | 32 ++++++++++++++++++++++++++++
> >  4 files changed, 87 insertions(+), 5 deletions(-)  create mode 100644
> > include/fsl_sleep.h
> >
> > diff --git a/common/board_f.c b/common/board_f.c index
> > e6aa298..b736d29 100644
> > --- a/common/board_f.c
> > +++ b/common/board_f.c
> > @@ -56,6 +56,9 @@
> >  #endif
> >  #include <dm/root.h>
> >  #include <linux/compiler.h>
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +#include <fsl_sleep.h>
> > +#endif
> >
> >  /*
> >   * Pointer to initial global data area @@ -921,6 +924,9 @@ static
> > init_fnc_t init_sequence_f[] = {  #if defined(CONFIG_MIPS) ||
> > defined(CONFIG_PPC)
> >      init_func_ram,
> >  #endif
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +   fsl_dp_resume,
> > +#endif
>
> Is there not an existing hook you can use here instead?  Is misc_init_f too early?
Misc_init_f is too early, we need to put it between DDR initialization and relocation.

> If we're going to add a new hook in here, it needs to be somewhat generically
> named, with the requirements of the system spelled out.
It is Freescale specific. Wouldn't be a misleading for other platforms that don't jump to kernel here?

> Some TI parts have a
> (setting aside marketing-speak) similar function and I believe the U-Boot patches
> for that use an existing hook to notice what happened and do what's needed.
Which function did you refer to? I can check if it can be used.

Thanks,
Yuantian

> Thanks!
>

> --
> Tom

[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[York Sun]

Let me take a deeper look.

York

-------- Original Message --------
From: Tang Yuantian-B29983
Sent: Wed, 22/10/2014 20:26
To: Sun York-R58495 ; Tom Rini
CC: albert.u.boot at aribaud.net; Jin Zhengxiong-R64188 ; u-boot at lists.denx.de
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

Thanks for your hint. Unfortunately I can't find such place.
It needs to be placed between DDR initialization and relocation.
It is used on both PPC and ARM platforms.
Do you have any sugguestions?

Thanks,
Yuantian

From: Sun York-R58495
Sent: Thursday, October 23, 2014 11:06 AM
To: Tang Yuantian-B29983; Tom Rini
Cc: albert.u.boot at aribaud.net; Jin Zhengxiong-R64188; u-boot at lists.denx.de
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms


Yuantian,

Tom didn't suggest a specific hook. If you can use existing one, you don't have to create a new one. It's preferred if you can find a good place in existing xxx_f functions.

York

-------- Original Message --------
From: Tang Yuantian-B29983
Sent: Wed, 22/10/2014 19:53
To: Tom Rini
CC: albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>; Jin Zhengxiong-R64188 ; u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>; Sun York-R58495
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

> -----Original Message-----
> From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Tom Rini
> Sent: Wednesday, October 22, 2014 9:54 PM
> To: Tang Yuantian-B29983
> Cc: albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>; Jin Zhengxiong-R64188; u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>;
> Sun York-R58495
> Subject: Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for
> Freescale QorIQ platforms
>
> On Sun, Sep 28, 2014 at 04:59:45PM +0800, Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>
> wrote:
> > From: Tang Yuantian <Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>>
> >
> > When Freescale QorIQ SoCs wake up from deep sleep, control is passed
> > to the primary core that starts executing uboot. After re-initialized
> > some IP blocks, like DDRC, kernel will take responsibility to continue
> > to restore environment it leaves before.
> >
> > This patch adds the deep sleep framework support for all Freescale
> > QorIQ platforms that use generic_board configuation.
> >
> > Signed-off-by: Tang Yuantian <Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>>
> > ---
> >  common/board_f.c               | 10 +++++++++
> >  drivers/ddr/fsl/arm_ddr_gen3.c | 48
> +++++++++++++++++++++++++++++++++++++-----
> >  include/fsl_ddr_sdram.h        |  2 ++
> >  include/fsl_sleep.h            | 32 ++++++++++++++++++++++++++++
> >  4 files changed, 87 insertions(+), 5 deletions(-)  create mode 100644
> > include/fsl_sleep.h
> >
> > diff --git a/common/board_f.c b/common/board_f.c index
> > e6aa298..b736d29 100644
> > --- a/common/board_f.c
> > +++ b/common/board_f.c
> > @@ -56,6 +56,9 @@
> >  #endif
> >  #include <dm/root.h>
> >  #include <linux/compiler.h>
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +#include <fsl_sleep.h>
> > +#endif
> >
> >  /*
> >   * Pointer to initial global data area @@ -921,6 +924,9 @@ static
> > init_fnc_t init_sequence_f[] = {  #if defined(CONFIG_MIPS) ||
> > defined(CONFIG_PPC)
> >      init_func_ram,
> >  #endif
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +   fsl_dp_resume,
> > +#endif
>
> Is there not an existing hook you can use here instead?  Is misc_init_f too early?
Misc_init_f is too early, we need to put it between DDR initialization and relocation.

> If we're going to add a new hook in here, it needs to be somewhat generically
> named, with the requirements of the system spelled out.
It is Freescale specific. Wouldn't be a misleading for other platforms that don't jump to kernel here?

> Some TI parts have a
> (setting aside marketing-speak) similar function and I believe the U-Boot patches
> for that use an existing hook to notice what happened and do what's needed.
Which function did you refer to? I can check if it can be used.

Thanks,
Yuantian

> Thanks!
>

> --
> Tom

[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[York Sun]

Yuantian,

I examined current code closely and have two suggestions:

1. In initdram() function, add a call to fsl_dp_resume()
It is rational because the deep sleep resume is mainly dealing with memory. Doing this means you need to add calls to all boards with deep sleep feature enabled, not a lot at this moment.
2. Add a new hook at exact location you proposed
But change to a more generic name, eg misc_ram. Add a weak function misc_ram() doing nothing. Then you can add misc_ram() in board file where it is needed.

Both require to put a hook in all boards with deep sleep enabled.

York



From: Tang Yuantian-B29983 <Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>>
Date: Wednesday, October 22, 2014 8:26 PM
To: York Sun <yorksun at freescale.com<mailto:yorksun@freescale.com>>, Tom Rini <trini at ti.com<mailto:trini@ti.com>>
Cc: "albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>" <albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>>, Jin Zhengxiong-R64188 <Jason.Jin at freescale.com<mailto:Jason.Jin@freescale.com>>, "u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>" <u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>>
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

Thanks for your hint. Unfortunately I can?t find such place.
It needs to be placed between DDR initialization and relocation.
It is used on both PPC and ARM platforms.
Do you have any sugguestions?

Thanks,
Yuantian

From: Sun York-R58495
Sent: Thursday, October 23, 2014 11:06 AM
To: Tang Yuantian-B29983; Tom Rini
Cc: albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>; Jin Zhengxiong-R64188; u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms


Yuantian,

Tom didn't suggest a specific hook. If you can use existing one, you don't have to create a new one. It's preferred if you can find a good place in existing xxx_f functions.

York

-------- Original Message --------
From: Tang Yuantian-B29983
Sent: Wed, 22/10/2014 19:53
To: Tom Rini
CC: albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>; Jin Zhengxiong-R64188 ; u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>; Sun York-R58495
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

> -----Original Message-----
> From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Tom Rini
> Sent: Wednesday, October 22, 2014 9:54 PM
> To: Tang Yuantian-B29983
> Cc: albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>; Jin Zhengxiong-R64188; u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>;
> Sun York-R58495
> Subject: Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for
> Freescale QorIQ platforms
>
> On Sun, Sep 28, 2014 at 04:59:45PM +0800, Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>
> wrote:
> > From: Tang Yuantian <Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>>
> >
> > When Freescale QorIQ SoCs wake up from deep sleep, control is passed
> > to the primary core that starts executing uboot. After re-initialized
> > some IP blocks, like DDRC, kernel will take responsibility to continue
> > to restore environment it leaves before.
> >
> > This patch adds the deep sleep framework support for all Freescale
> > QorIQ platforms that use generic_board configuation.
> >
> > Signed-off-by: Tang Yuantian <Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>>
> > ---
> >  common/board_f.c               | 10 +++++++++
> >  drivers/ddr/fsl/arm_ddr_gen3.c | 48
> +++++++++++++++++++++++++++++++++++++-----
> >  include/fsl_ddr_sdram.h        |  2 ++
> >  include/fsl_sleep.h            | 32 ++++++++++++++++++++++++++++
> >  4 files changed, 87 insertions(+), 5 deletions(-)  create mode 100644
> > include/fsl_sleep.h
> >
> > diff --git a/common/board_f.c b/common/board_f.c index
> > e6aa298..b736d29 100644
> > --- a/common/board_f.c
> > +++ b/common/board_f.c
> > @@ -56,6 +56,9 @@
> >  #endif
> >  #include <dm/root.h>
> >  #include <linux/compiler.h>
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +#include <fsl_sleep.h>
> > +#endif
> >
> >  /*
> >   * Pointer to initial global data area @@ -921,6 +924,9 @@ static
> > init_fnc_t init_sequence_f[] = {  #if defined(CONFIG_MIPS) ||
> > defined(CONFIG_PPC)
> >      init_func_ram,
> >  #endif
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +   fsl_dp_resume,
> > +#endif
>
> Is there not an existing hook you can use here instead?  Is misc_init_f too early?
Misc_init_f is too early, we need to put it between DDR initialization and relocation.

> If we're going to add a new hook in here, it needs to be somewhat generically
> named, with the requirements of the system spelled out.
It is Freescale specific. Wouldn't be a misleading for other platforms that don't jump to kernel here?

> Some TI parts have a
> (setting aside marketing-speak) similar function and I believe the U-Boot patches
> for that use an existing hook to notice what happened and do what's needed.
Which function did you refer to? I can check if it can be used.

Thanks,
Yuantian

> Thanks!
>

> --
> Tom

[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Yuantian Tang]

Thanks for your suggestions.
It sounds reasonable. I prefer the first one because we need to add calls in initdram() anyway.

Let's also take a look at what TI did and see if we can follow.

Thanks,
Yuantian

From: Sun York-R58495
Sent: Thursday, October 23, 2014 12:15 PM
To: Tang Yuantian-B29983; Tom Rini
Cc: albert.u.boot at aribaud.net; Jin Zhengxiong-R64188; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

Yuantian,

I examined current code closely and have two suggestions:

1. In initdram() function, add a call to fsl_dp_resume()
It is rational because the deep sleep resume is mainly dealing with memory. Doing this means you need to add calls to all boards with deep sleep feature enabled, not a lot at this moment.
2. Add a new hook at exact location you proposed
But change to a more generic name, eg misc_ram. Add a weak function misc_ram() doing nothing. Then you can add misc_ram() in board file where it is needed.

Both require to put a hook in all boards with deep sleep enabled.

York



From: Tang Yuantian-B29983 <Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>>
Date: Wednesday, October 22, 2014 8:26 PM
To: York Sun <yorksun at freescale.com<mailto:yorksun@freescale.com>>, Tom Rini <trini at ti.com<mailto:trini@ti.com>>
Cc: "albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>" <albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>>, Jin Zhengxiong-R64188 <Jason.Jin at freescale.com<mailto:Jason.Jin@freescale.com>>, "u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>" <u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>>
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

Thanks for your hint. Unfortunately I can't find such place.
It needs to be placed between DDR initialization and relocation.
It is used on both PPC and ARM platforms.
Do you have any sugguestions?

Thanks,
Yuantian

From: Sun York-R58495
Sent: Thursday, October 23, 2014 11:06 AM
To: Tang Yuantian-B29983; Tom Rini
Cc: albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>; Jin Zhengxiong-R64188; u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms


Yuantian,

Tom didn't suggest a specific hook. If you can use existing one, you don't have to create a new one. It's preferred if you can find a good place in existing xxx_f functions.

York

-------- Original Message --------
From: Tang Yuantian-B29983
Sent: Wed, 22/10/2014 19:53
To: Tom Rini
CC: albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>; Jin Zhengxiong-R64188 ; u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>; Sun York-R58495
Subject: RE: [U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

> -----Original Message-----
> From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Tom Rini
> Sent: Wednesday, October 22, 2014 9:54 PM
> To: Tang Yuantian-B29983
> Cc: albert.u.boot at aribaud.net<mailto:albert.u.boot@aribaud.net>; Jin Zhengxiong-R64188; u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>;
> Sun York-R58495
> Subject: Re: [U-Boot] [PATCH 1/4] Add deep sleep framework support for
> Freescale QorIQ platforms
>
> On Sun, Sep 28, 2014 at 04:59:45PM +0800, Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>
> wrote:
> > From: Tang Yuantian <Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>>
> >
> > When Freescale QorIQ SoCs wake up from deep sleep, control is passed
> > to the primary core that starts executing uboot. After re-initialized
> > some IP blocks, like DDRC, kernel will take responsibility to continue
> > to restore environment it leaves before.
> >
> > This patch adds the deep sleep framework support for all Freescale
> > QorIQ platforms that use generic_board configuation.
> >
> > Signed-off-by: Tang Yuantian <Yuantian.Tang at freescale.com<mailto:Yuantian.Tang@freescale.com>>
> > ---
> >  common/board_f.c               | 10 +++++++++
> >  drivers/ddr/fsl/arm_ddr_gen3.c | 48
> +++++++++++++++++++++++++++++++++++++-----
> >  include/fsl_ddr_sdram.h        |  2 ++
> >  include/fsl_sleep.h            | 32 ++++++++++++++++++++++++++++
> >  4 files changed, 87 insertions(+), 5 deletions(-)  create mode 100644
> > include/fsl_sleep.h
> >
> > diff --git a/common/board_f.c b/common/board_f.c index
> > e6aa298..b736d29 100644
> > --- a/common/board_f.c
> > +++ b/common/board_f.c
> > @@ -56,6 +56,9 @@
> >  #endif
> >  #include <dm/root.h>
> >  #include <linux/compiler.h>
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +#include <fsl_sleep.h>
> > +#endif
> >
> >  /*
> >   * Pointer to initial global data area @@ -921,6 +924,9 @@ static
> > init_fnc_t init_sequence_f[] = {  #if defined(CONFIG_MIPS) ||
> > defined(CONFIG_PPC)
> >      init_func_ram,
> >  #endif
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +   fsl_dp_resume,
> > +#endif
>
> Is there not an existing hook you can use here instead?  Is misc_init_f too early?
Misc_init_f is too early, we need to put it between DDR initialization and relocation.

> If we're going to add a new hook in here, it needs to be somewhat generically
> named, with the requirements of the system spelled out.
It is Freescale specific. Wouldn't be a misleading for other platforms that don't jump to kernel here?

> Some TI parts have a
> (setting aside marketing-speak) similar function and I believe the U-Boot patches
> for that use an existing hook to notice what happened and do what's needed.
Which function did you refer to? I can check if it can be used.

Thanks,
Yuantian

> Thanks!
>

> --
> Tom

[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Tom Rini]

On Thu, Oct 23, 2014 at 04:47:18AM +0000, Yuantian Tang wrote:

> Thanks for your suggestions.
> It sounds reasonable. I prefer the first one because we need to add calls in initdram() anyway.
> 
> Let's also take a look at what TI did and see if we can follow.

TI does it in SPL rather than full U-Boot but it's a similar location,
all things considered (in the part of SPL where we're dealing with SDRAM
init).

-- 
Tom
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