From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pavel Machek Date: Thu, 30 Oct 2014 12:22:57 +0100 Subject: [U-Boot] [PATCH] arm: socfpga: Add example config entry for EPCS/EPCQ SPI In-Reply-To: <1414661425-11842-1-git-send-email-marex@denx.de> References: <1414661425-11842-1-git-send-email-marex@denx.de> Message-ID: <20141030112257.GA2552@amd> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu 2014-10-30 10:30:25, Marek Vasut wrote: > Add example config file entry for the Altera SPI controller. This SPI > controller can also, under special conditions, be used to operate the > EPCS/EPCQ SPI NOR. > > Signed-off-by: Marek Vasut > Cc: Chin Liang See > Cc: Dinh Nguyen > Cc: Vince Bridgers Acked-by: Pavel Machek > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -79,6 +79,25 @@ > #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS > > /* > + * EPCS/EPCQx1 Serial Flash Controller > + */ > +#ifdef CONFIG_ALTERA_SPI > +#define CONFIG_CMD_SPI > +#define CONFIG_CMD_SF > +#define CONFIG_SF_DEFAULT_SPEED 30000000 > +#define CONFIG_SPI_FLASH > +#define CONFIG_SPI_FLASH_STMICRO > +#define CONFIG_SPI_FLASH_BAR > +/* > + * The base address is configurable in QSys, each board must specify the > + * base address based on it's particular FPGA configuration. Please note > + * that the address here is incremented by 0x400 from the Base address Are the double spaces around 0x400 intentional? Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html