[U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

Simon Glass
2014-11-07T18:01:37Z

Hi Stefan,

On 7 November 2014 05:50, Stefan Roese <sr@denx.de> wrote:
> This patch adds the driver for the Designware master SPI controller. This
> IP core is integrated on the Altera SoCFPGA. This implementation is a
> driver model (DM) implementation. So multiple SPI drivers can be used.
> Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
> used to connect the SPI NOR flashes. Without DM, using multiple SPI
> driver is not possible.
>
> This driver is very loosly based on the Linux driver. Most of the Linux
> driver is removed. Only the polling loop for the transfer is really used
> from this driver. As we don't support interrupts and DMA right now.
>
> This is tested on the SoCrates SoCFPGA board using the SPI pins on the
> P14 header.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

For driver model things:

Reviewed-by: Simon Glass <sjg@chromium.org>

Regards,
Simon