[U-Boot] [PATCH 0/6] arm: socfpga: Add Designware SPI support

[U-Boot] [PATCH 0/6] arm: socfpga: Add Designware SPI support

[Stefan Roese]

Hi!

This patchset adds the driver for the Designware master SPI controller.
This IP core is integrated on the Altera SoCFPGA. This implementation is a
driver model (DM) implementation. So multiple SPI drivers can be used.
Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
used to connect the SPI NOR flashes. Without DM, using multiple SPI
driver is not possible.

As mentioned above, this patchset depends on the SoCFPGA DT support. And
its also done on-top of the Cadence QSPI support I posted a short while
ago. But it doesn't depend on it. Its just that the patch series will
most likely generate merge conflicts if not applied in this sequence.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the
P14 header.

Thanks,
Stefan

Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

[U-Boot] [PATCH 1/6] arm: socfpga: Add DW master SPI clock to clock_manager.c

[Stefan Roese]

This function will be needed by the upcoming Designware master SPI
driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
---
 arch/arm/cpu/armv7/socfpga/clock_manager.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index d869f47..fa3b93a 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -507,6 +507,19 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
 	return clock;
 }
 
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	clock = cm_get_per_vco_clk_hz();
+
+	/* get the clock prior L4 SP divider (periph_base_clk) */
+	reg = readl(&clock_manager_base->per_pll.perbaseclk);
+	clock /= (reg + 1);
+
+	return clock;
+}
+
 static void cm_print_clock_quick_summary(void)
 {
 	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
@@ -518,6 +531,7 @@ static void cm_print_clock_quick_summary(void)
 	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
 	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
 	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+	printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
 }
 
 int set_cpu_clk_info(void)
-- 
2.1.3

[U-Boot] [PATCH 1/6] arm: socfpga: Add DW master SPI clock to clock_manager.c

[Marek Vasut]

On Friday, November 07, 2014 at 01:50:29 PM, Stefan Roese wrote:
> This function will be needed by the upcoming Designware master SPI
> driver.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>

Awww, was this missing ? Thanks!

Best regards,
Marek Vasut

[U-Boot] [PATCH 1/6] arm: socfpga: Add DW master SPI clock to clock_manager.c

[Pavel Machek]

On Fri 2014-11-07 13:50:29, Stefan Roese wrote:
> This function will be needed by the upcoming Designware master SPI
> driver.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>

Acked-by: Pavel Machek <pavel@denx.de>

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCH 2/6] arm: socfpga: Add socfpga_spim_enable() to reset_manager.c

[Stefan Roese]

This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.

This function is called from arch_early_init_r() if the SPI
driver is enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
---
 arch/arm/cpu/armv7/socfpga/misc.c                 | 6 ++++++
 arch/arm/cpu/armv7/socfpga/reset_manager.c        | 9 +++++++++
 arch/arm/include/asm/arch-socfpga/reset_manager.h | 3 +++
 3 files changed, 18 insertions(+)

diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index 8c3e5f7..73cffd3 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -202,6 +202,12 @@ int arch_early_init_r(void)
 
 	/* Add device descriptor to FPGA device table */
 	socfpga_fpga_add();
+
+#ifdef CONFIG_DESIGNWARE_SPI
+	/* Get Designware SPI controller out of reset */
+	socfpga_spim_enable();
+#endif
+
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index 1d3a95d..af9db85 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable)
 #endif
 	}
 }
+
+/* SPI Master enable (its held in reset by the preloader) */
+void socfpga_spim_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
+}
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 1857b80..034135b 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -14,6 +14,7 @@ void socfpga_bridges_reset(int enable);
 
 void socfpga_emac_reset(int enable);
 void socfpga_watchdog_reset(void);
+void socfpga_spim_enable(void);
 
 struct socfpga_reset_manager {
 	u32	status;
@@ -35,5 +36,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_PERMODRST_EMAC0_LSB	0
 #define RSTMGR_PERMODRST_EMAC1_LSB	1
 #define RSTMGR_PERMODRST_L4WD0_LSB	6
+#define RSTMGR_PERMODRST_SPIM0_LSB	18
+#define RSTMGR_PERMODRST_SPIM1_LSB	19
 
 #endif /* _RESET_MANAGER_H_ */
-- 
2.1.3

[U-Boot] [PATCH 2/6] arm: socfpga: Add socfpga_spim_enable() to reset_manager.c

[Pavel Machek]

On Fri 2014-11-07 13:50:30, Stefan Roese wrote:
> This function will be needed by the upcoming Designware master SPI
> driver. As the SPI master controller is held in reset by the current
> Preloader implementation. So we need to release the reset for the
> driver to communicate with the controller.
> 
> This function is called from arch_early_init_r() if the SPI
> driver is enabled.
> 
>  	}
>  }
> +
> +/* SPI Master enable (its held in reset by the preloader) */
> +void socfpga_spim_enable(void)
> +{
> +	const void *reset = &reset_manager_base->per_mod_reset;
> +
> +	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
> +	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);

Actually, you can do this with one clrbits, right?

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCH 2/6] arm: socfpga: Add socfpga_spim_enable() to reset_manager.c

[Stefan Roese]

On 12.11.2014 18:42, Pavel Machek wrote:
> On Fri 2014-11-07 13:50:30, Stefan Roese wrote:
>> This function will be needed by the upcoming Designware master SPI
>> driver. As the SPI master controller is held in reset by the current
>> Preloader implementation. So we need to release the reset for the
>> driver to communicate with the controller.
>>
>> This function is called from arch_early_init_r() if the SPI
>> driver is enabled.
>>
>>   	}
>>   }
>> +
>> +/* SPI Master enable (its held in reset by the preloader) */
>> +void socfpga_spim_enable(void)
>> +{
>> +	const void *reset = &reset_manager_base->per_mod_reset;
>> +
>> +	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
>> +	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
>
> Actually, you can do this with one clrbits, right?

Yes, will send a follow-up patch for this.

Thanks,
Stefan

[U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

[Stefan Roese]

This patch adds the driver for the Designware master SPI controller. This
IP core is integrated on the Altera SoCFPGA. This implementation is a
driver model (DM) implementation. So multiple SPI drivers can be used.
Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
used to connect the SPI NOR flashes. Without DM, using multiple SPI
driver is not possible.

This driver is very loosly based on the Linux driver. Most of the Linux
driver is removed. Only the polling loop for the transfer is really used
from this driver. As we don't support interrupts and DMA right now.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the
P14 header.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
---
 drivers/spi/Makefile         |   1 +
 drivers/spi/designware_spi.c | 425 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 426 insertions(+)
 create mode 100644 drivers/spi/designware_spi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 964fdc1..edbd520 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
 obj-$(CONFIG_CF_QSPI) += cf_qspi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
new file mode 100644
index 0000000..1bc0d04
--- /dev/null
+++ b/drivers/spi/designware_spi.c
@@ -0,0 +1,425 @@
+/*
+ * Designware master SPI core controller driver
+ *
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * Very loosly based on the Linux driver version which is:
+ * Copyright (c) 2009, Intel Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <spi.h>
+#include <fdtdec.h>
+#include <linux/compat.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offsets */
+#define DW_SPI_CTRL0			0x00
+#define DW_SPI_CTRL1			0x04
+#define DW_SPI_SSIENR			0x08
+#define DW_SPI_MWCR			0x0c
+#define DW_SPI_SER			0x10
+#define DW_SPI_BAUDR			0x14
+#define DW_SPI_TXFLTR			0x18
+#define DW_SPI_RXFLTR			0x1c
+#define DW_SPI_TXFLR			0x20
+#define DW_SPI_RXFLR			0x24
+#define DW_SPI_SR			0x28
+#define DW_SPI_IMR			0x2c
+#define DW_SPI_ISR			0x30
+#define DW_SPI_RISR			0x34
+#define DW_SPI_TXOICR			0x38
+#define DW_SPI_RXOICR			0x3c
+#define DW_SPI_RXUICR			0x40
+#define DW_SPI_MSTICR			0x44
+#define DW_SPI_ICR			0x48
+#define DW_SPI_DMACR			0x4c
+#define DW_SPI_DMATDLR			0x50
+#define DW_SPI_DMARDLR			0x54
+#define DW_SPI_IDR			0x58
+#define DW_SPI_VERSION			0x5c
+#define DW_SPI_DR			0x60
+
+/* Bit fields in CTRLR0 */
+#define SPI_DFS_OFFSET			0
+
+#define SPI_FRF_OFFSET			4
+#define SPI_FRF_SPI			0x0
+#define SPI_FRF_SSP			0x1
+#define SPI_FRF_MICROWIRE		0x2
+#define SPI_FRF_RESV			0x3
+
+#define SPI_MODE_OFFSET			6
+#define SPI_SCPH_OFFSET			6
+#define SPI_SCOL_OFFSET			7
+
+#define SPI_TMOD_OFFSET			8
+#define SPI_TMOD_MASK			(0x3 << SPI_TMOD_OFFSET)
+#define	SPI_TMOD_TR			0x0		/* xmit & recv */
+#define SPI_TMOD_TO			0x1		/* xmit only */
+#define SPI_TMOD_RO			0x2		/* recv only */
+#define SPI_TMOD_EPROMREAD		0x3		/* eeprom read mode */
+
+#define SPI_SLVOE_OFFSET		10
+#define SPI_SRL_OFFSET			11
+#define SPI_CFS_OFFSET			12
+
+/* Bit fields in SR, 7 bits */
+#define SR_MASK				0x7f		/* cover 7 bits */
+#define SR_BUSY				(1 << 0)
+#define SR_TF_NOT_FULL			(1 << 1)
+#define SR_TF_EMPT			(1 << 2)
+#define SR_RF_NOT_EMPT			(1 << 3)
+#define SR_RF_FULL			(1 << 4)
+#define SR_TX_ERR			(1 << 5)
+#define SR_DCOL				(1 << 6)
+
+#define RX_TIMEOUT			1000
+
+struct dw_spi_platdata {
+	s32 frequency;		/* Default clock frequency, -1 for none */
+	void __iomem *regs;
+};
+
+struct dw_spi_priv {
+	void __iomem *regs;
+	unsigned int freq;		/* Default frequency */
+	unsigned int mode;
+
+	int bits_per_word;
+	u8 cs;			/* chip select pin */
+	u8 n_bytes;		/* current is a 1/2/4 byte op */
+	u8 tmode;		/* TR/TO/RO/EEPROM */
+	u8 type;		/* SPI/SSP/MicroWire */
+	int len;
+
+	u32 fifo_len;		/* depth of the FIFO buffer */
+	void *tx;
+	void *tx_end;
+	void *rx;
+	void *rx_end;
+};
+
+static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset)
+{
+	return __raw_readl(priv->regs + offset);
+}
+
+static inline void dw_writel(struct dw_spi_priv *priv, u32 offset, u32 val)
+{
+	__raw_writel(val, priv->regs + offset);
+}
+
+static inline u16 dw_readw(struct dw_spi_priv *priv, u32 offset)
+{
+	return __raw_readw(priv->regs + offset);
+}
+
+static inline void dw_writew(struct dw_spi_priv *priv, u32 offset, u16 val)
+{
+	__raw_writew(val, priv->regs + offset);
+}
+
+static int dw_spi_ofdata_to_platdata(struct udevice *bus)
+{
+	struct dw_spi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = bus->of_offset;
+
+	plat->regs = (struct dw_spi *)fdtdec_get_addr(blob, node, "reg");
+
+	/* Use 500KHz as a suitable default */
+	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+					500000);
+	debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
+	      plat->frequency);
+
+	return 0;
+}
+
+static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
+{
+	dw_writel(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
+}
+
+/* Restart the controller, disable all interrupts, clean rx fifo */
+static void spi_hw_init(struct dw_spi_priv *priv)
+{
+	spi_enable_chip(priv, 0);
+	dw_writel(priv, DW_SPI_IMR, 0xff);
+	spi_enable_chip(priv, 1);
+
+	/*
+	 * Try to detect the FIFO depth if not set by interface driver,
+	 * the depth could be from 2 to 256 from HW spec
+	 */
+	if (!priv->fifo_len) {
+		u32 fifo;
+
+		for (fifo = 2; fifo <= 257; fifo++) {
+			dw_writew(priv, DW_SPI_TXFLTR, fifo);
+			if (fifo != dw_readw(priv, DW_SPI_TXFLTR))
+				break;
+		}
+
+		priv->fifo_len = (fifo == 257) ? 0 : fifo;
+		dw_writew(priv, DW_SPI_TXFLTR, 0);
+	}
+	debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
+}
+
+static int dw_spi_probe(struct udevice *bus)
+{
+	struct dw_spi_platdata *plat = dev_get_platdata(bus);
+	struct dw_spi_priv *priv = dev_get_priv(bus);
+
+	priv->regs = plat->regs;
+	priv->freq = plat->frequency;
+
+	/* Currently only bits_per_word == 8 supported */
+	priv->bits_per_word = 8;
+	priv->n_bytes = 1;
+
+	priv->tmode = 0; /* Tx & Rx */
+
+	/* Basic HW init */
+	spi_hw_init(priv);
+
+	return 0;
+}
+
+/* Return the max entries we can fill into tx fifo */
+static inline u32 tx_max(struct dw_spi_priv *priv)
+{
+	u32 tx_left, tx_room, rxtx_gap;
+
+	tx_left = (priv->tx_end - priv->tx) / priv->n_bytes;
+	tx_room = priv->fifo_len - dw_readw(priv, DW_SPI_TXFLR);
+
+	/*
+	 * Another concern is about the tx/rx mismatch, we
+	 * though to use (priv->fifo_len - rxflr - txflr) as
+	 * one maximum value for tx, but it doesn't cover the
+	 * data which is out of tx/rx fifo and inside the
+	 * shift registers. So a control from sw point of
+	 * view is taken.
+	 */
+	rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
+		priv->n_bytes;
+
+	return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
+}
+
+/* Return the max entries we should read out of rx fifo */
+static inline u32 rx_max(struct dw_spi_priv *priv)
+{
+	u32 rx_left = (priv->rx_end - priv->rx) / priv->n_bytes;
+
+	return min_t(u32, rx_left, dw_readw(priv, DW_SPI_RXFLR));
+}
+
+static void dw_writer(struct dw_spi_priv *priv)
+{
+	u32 max = tx_max(priv);
+	u16 txw = 0;
+
+	while (max--) {
+		/* Set the tx word if the transfer's original "tx" is not null */
+		if (priv->tx_end - priv->len) {
+			if (priv->n_bytes == 1)
+				txw = *(u8 *)(priv->tx);
+			else
+				txw = *(u16 *)(priv->tx);
+		}
+		dw_writew(priv, DW_SPI_DR, txw);
+		debug("%s: tx=0x%02x\n", __func__, txw);
+		priv->tx += priv->n_bytes;
+	}
+}
+
+static int dw_reader(struct dw_spi_priv *priv)
+{
+	unsigned start = get_timer(0);
+	u32 max;
+	u16 rxw;
+
+	/* Wait for rx data to be ready */
+	while (rx_max(priv) == 0) {
+		if (get_timer(start) > RX_TIMEOUT)
+			return -ETIMEDOUT;
+	}
+
+	max = rx_max(priv);
+
+	while (max--) {
+		rxw = dw_readw(priv, DW_SPI_DR);
+		debug("%s: rx=0x%02x\n", __func__, rxw);
+		/* Care rx only if the transfer's original "rx" is not null */
+		if (priv->rx_end - priv->len) {
+			if (priv->n_bytes == 1)
+				*(u8 *)(priv->rx) = rxw;
+			else
+				*(u16 *)(priv->rx) = rxw;
+		}
+		priv->rx += priv->n_bytes;
+	}
+
+	return 0;
+}
+
+static int poll_transfer(struct dw_spi_priv *priv)
+{
+	int ret;
+
+	do {
+		dw_writer(priv);
+		ret = dw_reader(priv);
+		if (ret < 0)
+			return ret;
+	} while (priv->rx_end > priv->rx);
+
+	return 0;
+}
+
+static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		       const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct dw_spi_priv *priv = dev_get_priv(bus);
+	const u8 *tx = dout;
+	u8 *rx = din;
+	int ret = 0;
+	u32 cr0 = 0;
+	u8 bits = 0;
+	u32 cs;
+
+	/* spi core configured to do 8 bit transfers */
+	if (bitlen % 8) {
+		debug("Non byte aligned SPI transfer.\n");
+		return -1;
+	}
+
+	bits = priv->bits_per_word;
+	priv->n_bytes = bits >> 3;
+	cr0 = (bits - 1) | (priv->type << SPI_FRF_OFFSET) |
+		(priv->mode << SPI_MODE_OFFSET) |
+		(priv->tmode << SPI_TMOD_OFFSET);
+
+	if (rx && tx)
+		priv->tmode = SPI_TMOD_TR;
+	else if (rx)
+		priv->tmode = SPI_TMOD_RO;
+	else
+		priv->tmode = SPI_TMOD_TO;
+
+	cr0 &= ~SPI_TMOD_MASK;
+	cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
+
+	priv->len = bitlen / 8;
+	debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
+
+	priv->tx = (void *)tx;
+	priv->tx_end = priv->tx + priv->len;
+	priv->rx = rx;
+	priv->rx_end = priv->rx + priv->len;
+
+	/* Disable controller before writing control registers */
+	spi_enable_chip(priv, 0);
+
+	debug("%s: cr0=%08x\n", __func__, cr0);
+	/* Reprogram cr0 only if changed */
+	if (dw_readw(priv, DW_SPI_CTRL0) != cr0)
+		dw_writew(priv, DW_SPI_CTRL0, cr0);
+
+	/*
+	 * Configure the desired SS (slave select 0...3) in the controller
+	 * The DW SPI controller will activate and deactivate this CS
+	 * automatically. So no cs_activate() etc is needed in this driver.
+	 */
+	cs = spi_chip_select(dev);
+	dw_writel(priv, DW_SPI_SER, 1 << cs);
+
+	/* Enable controller after writing control registers */
+	spi_enable_chip(priv, 1);
+
+	/* Start transfer in a polling loop */
+	ret = poll_transfer(priv);
+
+	return ret;
+}
+
+static int dw_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct dw_spi_platdata *plat = bus->platdata;
+	struct dw_spi_priv *priv = dev_get_priv(bus);
+	u16 clk_div;
+
+	if (speed > plat->frequency)
+		speed = plat->frequency;
+
+	/* Disable controller before writing control registers */
+	spi_enable_chip(priv, 0);
+
+	/* clk_div doesn't support odd number */
+	clk_div = CONFIG_DW_SPI_REF_CLK / speed;
+	clk_div = (clk_div + 1) & 0xfffe;
+	dw_writel(priv, DW_SPI_BAUDR, clk_div);
+
+	/* Enable controller after writing control registers */
+	spi_enable_chip(priv, 1);
+
+	priv->freq = speed;
+	debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
+	      priv->freq, clk_div);
+
+	return 0;
+}
+
+static int dw_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct dw_spi_priv *priv = dev_get_priv(bus);
+
+	/*
+	 * Can't set mode yet. Since this depends on if rx, tx, or
+	 * rx & tx is requested. So we have to defer this to the
+	 * real transfer function.
+	 */
+	priv->mode = mode;
+	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+	return 0;
+}
+
+static const struct dm_spi_ops dw_spi_ops = {
+	.xfer		= dw_spi_xfer,
+	.set_speed	= dw_spi_set_speed,
+	.set_mode	= dw_spi_set_mode,
+	/*
+	 * cs_info is not needed, since we require all chip selects to be
+	 * in the device tree explicitly
+	 */
+};
+
+static const struct udevice_id dw_spi_ids[] = {
+	{ .compatible = "snps,dw-spi-mmio" },
+	{ }
+};
+
+U_BOOT_DRIVER(dw_spi) = {
+	.name = "dw_spi",
+	.id = UCLASS_SPI,
+	.of_match = dw_spi_ids,
+	.ops = &dw_spi_ops,
+	.ofdata_to_platdata = dw_spi_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
+	.priv_auto_alloc_size = sizeof(struct dw_spi_priv),
+	.per_child_auto_alloc_size = sizeof(struct spi_slave),
+	.probe = dw_spi_probe,
+};
-- 
2.1.3

[U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

[Marek Vasut]

On Friday, November 07, 2014 at 01:50:31 PM, Stefan Roese wrote:
> This patch adds the driver for the Designware master SPI controller. This
> IP core is integrated on the Altera SoCFPGA. This implementation is a
> driver model (DM) implementation. So multiple SPI drivers can be used.
> Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
> used to connect the SPI NOR flashes. Without DM, using multiple SPI
> driver is not possible.
> 
> This driver is very loosly based on the Linux driver. Most of the Linux
> driver is removed. Only the polling loop for the transfer is really used
> from this driver. As we don't support interrupts and DMA right now.
> 
> This is tested on the SoCrates SoCFPGA board using the SPI pins on the
> P14 header.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

[...]

> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
> new file mode 100644
> index 0000000..1bc0d04
> --- /dev/null
> +++ b/drivers/spi/designware_spi.c
> @@ -0,0 +1,425 @@
> +/*
> + * Designware master SPI core controller driver
> + *
> + * Copyright (C) 2014 Stefan Roese <sr@denx.de>
> + *
> + * Very loosly based on the Linux driver version which is:
> + * Copyright (c) 2009, Intel Corporation.
> + *
> + * SPDX-License-Identifier:	GPL-2.0

What's the agreement about the licensing now, GPL-2.0 or GPL-2.0+ ?

[...]

> +static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset)
> +{
> +	return __raw_readl(priv->regs + offset);
> +}

Do we really need these wrappers ?

[...]

Thanks!

[U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

[Simon Glass]

Hi Stefan,

On 7 November 2014 05:50, Stefan Roese <sr@denx.de> wrote:
> This patch adds the driver for the Designware master SPI controller. This
> IP core is integrated on the Altera SoCFPGA. This implementation is a
> driver model (DM) implementation. So multiple SPI drivers can be used.
> Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
> used to connect the SPI NOR flashes. Without DM, using multiple SPI
> driver is not possible.
>
> This driver is very loosly based on the Linux driver. Most of the Linux
> driver is removed. Only the polling loop for the transfer is really used
> from this driver. As we don't support interrupts and DMA right now.
>
> This is tested on the SoCrates SoCFPGA board using the SPI pins on the
> P14 header.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

For driver model things:

Reviewed-by: Simon Glass <sjg@chromium.org>

Regards,
Simon

[U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

[Pavel Machek]

Hi!

You tripped my spell-checker, sorry.

> This patch adds the driver for the Designware master SPI controller. This
> IP core is integrated on the Altera SoCFPGA. This implementation is a
> driver model (DM) implementation. So multiple SPI drivers can be used.
> Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
> used to connect the SPI NOR flashes. Without DM, using multiple SPI
> driver is not possible.

drivers.

> This driver is very loosly based on the Linux driver. Most of the

loosely?

> driver is removed. Only the polling loop for the transfer is really used
> from this driver. As we don't support interrupts and DMA right now.

, as


> + * Very loosly based on the Linux driver version which is:

loosely. (And citing filename here might be useful.)
> +
> +/* Register offsets */
> +#define DW_SPI_CTRL0			0x00
> +#define DW_SPI_CTRL1			0x04
> +#define DW_SPI_SSIENR			0x08
> +#define DW_SPI_MWCR			0x0c
> +#define DW_SPI_SER			0x10
> +#define DW_SPI_BAUDR			0x14
> +#define DW_SPI_TXFLTR			0x18
> +#define DW_SPI_RXFLTR			0x1c
> +#define DW_SPI_TXFLR			0x20
> +#define DW_SPI_RXFLR			0x24
> +#define DW_SPI_SR			0x28
> +#define DW_SPI_IMR			0x2c
> +#define DW_SPI_ISR			0x30
> +#define DW_SPI_RISR			0x34
> +#define DW_SPI_TXOICR			0x38
> +#define DW_SPI_RXOICR			0x3c
> +#define DW_SPI_RXUICR			0x40
> +#define DW_SPI_MSTICR			0x44
> +#define DW_SPI_ICR			0x48
> +#define DW_SPI_DMACR			0x4c
> +#define DW_SPI_DMATDLR			0x50
> +#define DW_SPI_DMARDLR			0x54
> +#define DW_SPI_IDR			0x58
> +#define DW_SPI_VERSION			0x5c
> +#define DW_SPI_DR			0x60

Any chance to convert this to structure?

> +#define RX_TIMEOUT			1000

comment with units would be welcome.
 
> +
> +struct dw_spi_platdata {
> +	s32 frequency;		/* Default clock frequency, -1 for none */
> +	void __iomem *regs;
> +};
> +
> +struct dw_spi_priv {
> +	void __iomem *regs;
> +	unsigned int freq;		/* Default frequency */
> +	unsigned int mode;
> +
> +	int bits_per_word;
> +	u8 cs;			/* chip select pin */
> +	u8 n_bytes;		/* current is a 1/2/4 byte op */
> +	u8 tmode;		/* TR/TO/RO/EEPROM */
> +	u8 type;		/* SPI/SSP/MicroWire */
> +	int len;

Having both n_bytes and len is "interesting". Turn n_bytes into
"word_size"?

> +static int dw_spi_probe(struct udevice *bus)
> +{
> +	struct dw_spi_platdata *plat = dev_get_platdata(bus);
> +	struct dw_spi_priv *priv = dev_get_priv(bus);
> +
> +	priv->regs = plat->regs;
> +	priv->freq = plat->frequency;
> +
> +	/* Currently only bits_per_word == 8 supported */
> +	priv->bits_per_word = 8;
> +	priv->n_bytes = 1;

n_bytes -> bytes_per_word? Why we have two variables for same
information?

> +	/*
> +	 * Another concern is about the tx/rx mismatch, we
> +	 * though to use (priv->fifo_len - rxflr - txflr) as

"thought about using"?


> +	while (max--) {
> +		rxw = dw_readw(priv, DW_SPI_DR);
> +		debug("%s: rx=0x%02x\n", __func__, rxw);
> +		/* Care rx only if the transfer's original "rx" is not null */

"Care about"?
> +
> +	/* spi core configured to do 8 bit transfers */

"core is"?

Thanks,
									Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

[Marek Vasut]

On Wednesday, November 12, 2014 at 06:51:42 PM, Pavel Machek wrote:
> Hi!
> 
> You tripped my spell-checker, sorry.
> 
> > This patch adds the driver for the Designware master SPI controller. This
> > IP core is integrated on the Altera SoCFPGA. This implementation is a
> > driver model (DM) implementation. So multiple SPI drivers can be used.
> > Thats necessary, since SoCFPGA also integrates the Cadence QSPI
> > controller used to connect the SPI NOR flashes. Without DM, using
> > multiple SPI driver is not possible.
> 
> drivers.
> 
> > This driver is very loosly based on the Linux driver. Most of the
> 
> loosely?
> 
> > driver is removed. Only the polling loop for the transfer is really used
> > from this driver. As we don't support interrupts and DMA right now.
> 
> , as
> 
> > + * Very loosly based on the Linux driver version which is:
> loosely. (And citing filename here might be useful.)

I fixed the text and I placed this whole driver patchset to

u-boot-socfpga:topic/drivers/spi-20141114

Can you please fix the code so I can replace that one patch ? Or just
send me one which I can squash into this patch, either way works.

Thanks!

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

[Stefan Roese]

On 14.11.2014 21:16, Marek Vasut wrote:
> On Wednesday, November 12, 2014 at 06:51:42 PM, Pavel Machek wrote:
>> Hi!
>>
>> You tripped my spell-checker, sorry.
>>
>>> This patch adds the driver for the Designware master SPI controller. This
>>> IP core is integrated on the Altera SoCFPGA. This implementation is a
>>> driver model (DM) implementation. So multiple SPI drivers can be used.
>>> Thats necessary, since SoCFPGA also integrates the Cadence QSPI
>>> controller used to connect the SPI NOR flashes. Without DM, using
>>> multiple SPI driver is not possible.
>>
>> drivers.
>>
>>> This driver is very loosly based on the Linux driver. Most of the
>>
>> loosely?
>>
>>> driver is removed. Only the polling loop for the transfer is really used
>>> from this driver. As we don't support interrupts and DMA right now.
>>
>> , as
>>
>>> + * Very loosly based on the Linux driver version which is:
>> loosely. (And citing filename here might be useful.)
>
> I fixed the text and I placed this whole driver patchset to
>
> u-boot-socfpga:topic/drivers/spi-20141114
>
> Can you please fix the code so I can replace that one patch ? Or just
> send me one which I can squash into this patch, either way works.

Yes. I'll take a look at it tomorrow or on Monday.

Thanks,
Stefan

[U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

[Marek Vasut]

On Saturday, November 15, 2014 at 02:33:27 PM, Stefan Roese wrote:
> On 14.11.2014 21:16, Marek Vasut wrote:
> > On Wednesday, November 12, 2014 at 06:51:42 PM, Pavel Machek wrote:
> >> Hi!
> >> 
> >> You tripped my spell-checker, sorry.
> >> 
> >>> This patch adds the driver for the Designware master SPI controller.
> >>> This IP core is integrated on the Altera SoCFPGA. This implementation
> >>> is a driver model (DM) implementation. So multiple SPI drivers can be
> >>> used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI
> >>> controller used to connect the SPI NOR flashes. Without DM, using
> >>> multiple SPI driver is not possible.
> >> 
> >> drivers.
> >> 
> >>> This driver is very loosly based on the Linux driver. Most of the
> >> 
> >> loosely?
> >> 
> >>> driver is removed. Only the polling loop for the transfer is really
> >>> used from this driver. As we don't support interrupts and DMA right
> >>> now.
> >> 
> >> , as
> >> 
> >>> + * Very loosly based on the Linux driver version which is:
> >> loosely. (And citing filename here might be useful.)
> > 
> > I fixed the text and I placed this whole driver patchset to
> > 
> > u-boot-socfpga:topic/drivers/spi-20141114
> > 
> > Can you please fix the code so I can replace that one patch ? Or just
> > send me one which I can squash into this patch, either way works.
> 
> Yes. I'll take a look at it tomorrow or on Monday.

Thank you !

Best regards,
Marek Vasut

[U-Boot] [PATCH 4/6] arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devices

[Stefan Roese]

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
---
 arch/arm/dts/socfpga.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 4a789a9..9de7ca9 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -654,6 +654,34 @@
 			status = "disabled";
 		};
 
+		spi0: spi at fff00000 {
+			compatible = "snps,dw-spi-mmio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfff00000 0x1000>;
+			interrupts = <0 154 4>;
+			num-chipselect = <4>;
+			bus-num = <0>;
+			tx-dma-channel = <&pdma 16>;
+			rx-dma-channel = <&pdma 17>;
+			clocks = <&per_base_clk>;
+			status = "disabled";
+		};
+
+		spi1: spi at fff01000 {
+			compatible = "snps,dw-spi-mmio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfff01000 0x1000>;
+			interrupts = <0 156 4>;
+			num-chipselect = <4>;
+			bus-num = <1>;
+			tx-dma-channel = <&pdma 20>;
+			rx-dma-channel = <&pdma 21>;
+			clocks = <&per_base_clk>;
+			status = "disabled";
+		};
+
 		/* Local timer */
 		timer at fffec600 {
 			compatible = "arm,cortex-a9-twd-timer";
-- 
2.1.3

[U-Boot] [PATCH 4/6] arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devices

[Pavel Machek]

On Fri 2014-11-07 13:50:32, Stefan Roese wrote:
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>

Acked-by: Pavel Machek <pavel@denx.de>

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCH 5/6] arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing

[Stefan Roese]

Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct for the Designware SPI
controllers.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
---
 arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 02bb8b3..4f0bfab 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -27,6 +27,8 @@
 
  	aliases {
 		spi0 = "/spi at ff705000";		/* QSPI */
+		spi1 = "/spi at fff00000";
+		spi2 = "/spi at fff01000";
  	};
 
 	memory {
-- 
2.1.3

[U-Boot] [PATCH 5/6] arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing

[Pavel Machek]

On Fri 2014-11-07 13:50:33, Stefan Roese wrote:
> Without this alias, DM based probing does not work. So lets add this
> alias to get the bus numbering correct for the Designware SPI
> controllers.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>

Acked-by: Pavel Machek <pavel@denx.de>

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCH 6/6] arm: socfpga: Add Designware (DW) SPI support to config header

[Stefan Roese]

Enable support for the DW master SPI controller in the config header
for the SoCFPGA. This controller can only be enabled, if DT support
is enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
---
 include/configs/socfpga_common.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 9fc4212..830b956 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -191,6 +191,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_CMD_SF
 #endif
 
+#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DESIGNWARE_SPI
+#ifndef __ASSEMBLY__
+unsigned int cm_get_spi_controller_clk_hz(void);
+#define CONFIG_DW_SPI_REF_CLK		cm_get_spi_controller_clk_hz()
+#endif
+#define CONFIG_CMD_SPI
+#endif
+
 /*
  * Serial Driver
  */
-- 
2.1.3

[U-Boot] [PATCH 6/6] arm: socfpga: Add Designware (DW) SPI support to config header

[Pavel Machek]

On Fri 2014-11-07 13:50:34, Stefan Roese wrote:
> Enable support for the DW master SPI controller in the config header
> for the SoCFPGA. This controller can only be enabled, if DT support
> is enabled.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> ---
>  include/configs/socfpga_common.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index 9fc4212..830b956 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -191,6 +191,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>  #define CONFIG_CMD_SF
>  #endif
>  
> +#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
> +#define CONFIG_CMD_DM
> +#define CONFIG_DM
> +#define CONFIG_DM_SPI
> +#define CONFIG_DESIGNWARE_SPI
> +#ifndef __ASSEMBLY__
> +unsigned int cm_get_spi_controller_clk_hz(void);
> +#define CONFIG_DW_SPI_REF_CLK		cm_get_spi_controller_clk_hz()

Putting prototypes into configuration file is ugly. Hiding function
call into macro so that it looks like constant is evil. Is there
better solution?
									Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCH 6/6] arm: socfpga: Add Designware (DW) SPI support to config header

[Marek Vasut]

On Wednesday, November 12, 2014 at 06:53:54 PM, Pavel Machek wrote:
> On Fri 2014-11-07 13:50:34, Stefan Roese wrote:
> > Enable support for the DW master SPI controller in the config header
> > for the SoCFPGA. This controller can only be enabled, if DT support
> > is enabled.
> > 
> > Signed-off-by: Stefan Roese <sr@denx.de>
> > Cc: Chin Liang See <clsee@altera.com>
> > Cc: Dinh Nguyen <dinguyen@altera.com>
> > Cc: Vince Bridgers <vbridger@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Pavel Machek <pavel@denx.de>
> > ---
> > 
> >  include/configs/socfpga_common.h | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h index 9fc4212..830b956 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -191,6 +191,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> > 
> >  #define CONFIG_CMD_SF
> >  #endif
> > 
> > +#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
> > +#define CONFIG_CMD_DM
> > +#define CONFIG_DM
> > +#define CONFIG_DM_SPI
> > +#define CONFIG_DESIGNWARE_SPI
> > +#ifndef __ASSEMBLY__
> > +unsigned int cm_get_spi_controller_clk_hz(void);
> > +#define CONFIG_DW_SPI_REF_CLK		cm_get_spi_controller_clk_hz()
> 
> Putting prototypes into configuration file is ugly. Hiding function
> call into macro so that it looks like constant is evil. Is there
> better solution?

The SPI driver should call this function directly. Or is there a reason why
such a macro is used ?

Best regards,
Marek Vasut

[U-Boot] [PATCH 6/6] arm: socfpga: Add Designware (DW) SPI support to config header

[Stefan Roese]

On 14.11.2014 21:18, Marek Vasut wrote:
> On Wednesday, November 12, 2014 at 06:53:54 PM, Pavel Machek wrote:
>> On Fri 2014-11-07 13:50:34, Stefan Roese wrote:
>>> Enable support for the DW master SPI controller in the config header
>>> for the SoCFPGA. This controller can only be enabled, if DT support
>>> is enabled.
>>>
>>> Signed-off-by: Stefan Roese <sr@denx.de>
>>> Cc: Chin Liang See <clsee@altera.com>
>>> Cc: Dinh Nguyen <dinguyen@altera.com>
>>> Cc: Vince Bridgers <vbridger@altera.com>
>>> Cc: Marek Vasut <marex@denx.de>
>>> Cc: Pavel Machek <pavel@denx.de>
>>> ---
>>>
>>>   include/configs/socfpga_common.h | 12 ++++++++++++
>>>   1 file changed, 12 insertions(+)
>>>
>>> diff --git a/include/configs/socfpga_common.h
>>> b/include/configs/socfpga_common.h index 9fc4212..830b956 100644
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -191,6 +191,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>>>
>>>   #define CONFIG_CMD_SF
>>>   #endif
>>>
>>> +#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
>>> +#define CONFIG_CMD_DM
>>> +#define CONFIG_DM
>>> +#define CONFIG_DM_SPI
>>> +#define CONFIG_DESIGNWARE_SPI
>>> +#ifndef __ASSEMBLY__
>>> +unsigned int cm_get_spi_controller_clk_hz(void);
>>> +#define CONFIG_DW_SPI_REF_CLK		cm_get_spi_controller_clk_hz()
>>
>> Putting prototypes into configuration file is ugly. Hiding function
>> call into macro so that it looks like constant is evil. Is there
>> better solution?
>
> The SPI driver should call this function directly. Or is there a reason why
> such a macro is used ?

Historically. I'll check it again and will implement it differently in 
the next version. Tomorrow or on Monday.

Thanks,
Stefan

[U-Boot] [PATCH 6/6] arm: socfpga: Add Designware (DW) SPI support to config header

[Marek Vasut]

On Saturday, November 15, 2014 at 02:35:03 PM, Stefan Roese wrote:
> On 14.11.2014 21:18, Marek Vasut wrote:
> > On Wednesday, November 12, 2014 at 06:53:54 PM, Pavel Machek wrote:
> >> On Fri 2014-11-07 13:50:34, Stefan Roese wrote:
> >>> Enable support for the DW master SPI controller in the config header
> >>> for the SoCFPGA. This controller can only be enabled, if DT support
> >>> is enabled.
> >>> 
> >>> Signed-off-by: Stefan Roese <sr@denx.de>
> >>> Cc: Chin Liang See <clsee@altera.com>
> >>> Cc: Dinh Nguyen <dinguyen@altera.com>
> >>> Cc: Vince Bridgers <vbridger@altera.com>
> >>> Cc: Marek Vasut <marex@denx.de>
> >>> Cc: Pavel Machek <pavel@denx.de>
> >>> ---
> >>> 
> >>>   include/configs/socfpga_common.h | 12 ++++++++++++
> >>>   1 file changed, 12 insertions(+)
> >>> 
> >>> diff --git a/include/configs/socfpga_common.h
> >>> b/include/configs/socfpga_common.h index 9fc4212..830b956 100644
> >>> --- a/include/configs/socfpga_common.h
> >>> +++ b/include/configs/socfpga_common.h
> >>> @@ -191,6 +191,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> >>> 
> >>>   #define CONFIG_CMD_SF
> >>>   #endif
> >>> 
> >>> +#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
> >>> +#define CONFIG_CMD_DM
> >>> +#define CONFIG_DM
> >>> +#define CONFIG_DM_SPI
> >>> +#define CONFIG_DESIGNWARE_SPI
> >>> +#ifndef __ASSEMBLY__
> >>> +unsigned int cm_get_spi_controller_clk_hz(void);
> >>> +#define CONFIG_DW_SPI_REF_CLK		cm_get_spi_controller_clk_hz()
> >> 
> >> Putting prototypes into configuration file is ugly. Hiding function
> >> call into macro so that it looks like constant is evil. Is there
> >> better solution?
> > 
> > The SPI driver should call this function directly. Or is there a reason
> > why such a macro is used ?
> 
> Historically. I'll check it again and will implement it differently in
> the next version. Tomorrow or on Monday.

Roger. Thank you!

Best regards,
Marek Vasut