From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Fri, 14 Nov 2014 09:00:26 +0100 Subject: [U-Boot] [PATCH v3 22/30] ARM: cache_v7: Various minor cleanups In-Reply-To: <1415842036-28471-23-git-send-email-sjg@chromium.org> References: <1415842036-28471-1-git-send-email-sjg@chromium.org> <1415842036-28471-23-git-send-email-sjg@chromium.org> Message-ID: <20141114090026.066ff35f@lilith> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hello Simon, I've actually applied v2 of this patch and PRed it to u-boot/master) and accidentally not acked it. Apologies. On Wed, 12 Nov 2014 18:27:08 -0700, Simon Glass wrote: > From: Thierry Reding > > Remove two gratuituous blank lines, uses u32 (instead of int) as the > type for values that will be written to a register, moves the beginning > of the variable declaration section to a separate line (rather than the > one with the opening brace) and keeps the function signature on a single > line where possible. > > Signed-off-by: Thierry Reding > Acked-by: Simon Glass > Signed-off-by: Simon Glass > --- > > Changes in v3: None > > arch/arm/cpu/armv7/cache_v7.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c > index a2c4032..0f9d837 100644 > --- a/arch/arm/cpu/armv7/cache_v7.c > +++ b/arch/arm/cpu/armv7/cache_v7.c > @@ -21,7 +21,8 @@ > * to get size details from Current Cache Size ID Register(CCSIDR) > */ > static void set_csselr(u32 level, u32 type) > -{ u32 csselr = level << 1 | type; > +{ > + u32 csselr = level << 1 | type; > > /* Write to Cache Size Selection Register(CSSELR) */ > asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); > @@ -49,7 +50,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, > u32 num_ways, u32 way_shift, > u32 log2_line_len) > { > - int way, set, setway; > + int way, set; > + u32 setway; > > /* > * For optimal assembly code: > @@ -73,7 +75,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, > u32 num_ways, u32 way_shift, > u32 log2_line_len) > { > - int way, set, setway; > + int way, set; > + u32 setway; > > /* > * For optimal assembly code: > @@ -134,7 +137,6 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation) > static void v7_maint_dcache_all(u32 operation) > { > u32 level, cache_type, level_start_bit = 0; > - > u32 clidr = get_clidr(); > > for (level = 0; level < 7; level++) { > @@ -147,8 +149,7 @@ static void v7_maint_dcache_all(u32 operation) > } > } > > -static void v7_dcache_clean_inval_range(u32 start, > - u32 stop, u32 line_len) > +static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len) > { > u32 mva; > > @@ -256,7 +257,6 @@ void flush_dcache_all(void) > */ > void invalidate_dcache_range(unsigned long start, unsigned long stop) > { > - > v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); > > v7_outer_cache_inval_range(start, stop); > -- > 2.1.0.rc2.206.gedb03e5 > Amicalement, -- Albert.