[U-Boot] [PATCH v3 23/30] ARM: cache-cp15: Use more accurate types

[Albert ARIBAUD <albert.u.boot@aribaud.net>]

Hello Simon,

I've actually applied v2 of this patch and PRed it to u-boot/master)
and accidentally not acked it.

Apologies.

On Wed, 12 Nov 2014 18:27:09 -0700, Simon Glass <sjg@chromium.org>
wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> size_t is the canonical type to represent variables that contain a size.
> Use it instead of signed integer. Physical addresses can be larger than
> 32-bit, so use a more appropriate type for them as well. phys_addr_t is
> a type that is 32-bit on systems that use 32-bit addresses and 64-bit if
> the system is 64-bit or uses a form of physical address extension to use
> a larger address space on 32-bit systems. Using these types the same API
> can be implemented on a wider range of systems.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
> Changes in v3: None
> 
>  arch/arm/include/asm/system.h | 2 +-
>  arch/arm/lib/cache-cp15.c     | 6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
> index ca2d44f..61e2914 100644
> --- a/arch/arm/include/asm/system.h
> +++ b/arch/arm/include/asm/system.h
> @@ -201,7 +201,7 @@ enum {
>   * \param size		size of memory region to change
>   * \param option	dcache option to select
>   */
> -void mmu_set_region_dcache_behaviour(u32 start, int size,
> +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
>  				     enum dcache_option option);
>  
>  /**
> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> index 2155fe8..0291afa 100644
> --- a/arch/arm/lib/cache-cp15.c
> +++ b/arch/arm/lib/cache-cp15.c
> @@ -47,15 +47,15 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
>  	debug("%s: Warning: not implemented\n", __func__);
>  }
>  
> -void mmu_set_region_dcache_behaviour(u32 start, int size,
> +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
>  				     enum dcache_option option)
>  {
>  	u32 *page_table = (u32 *)gd->arch.tlb_addr;
> -	u32 upto, end;
> +	unsigned long upto, end;
>  
>  	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
>  	start = start >> MMU_SECTION_SHIFT;
> -	debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
> +	debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
>  	      option);
>  	for (upto = start; upto < end; upto++)
>  		set_section_dcache(upto, option);
> -- 
> 2.1.0.rc2.206.gedb03e5
> 



Amicalement,
-- 
Albert.