[U-Boot] [PATCH 4/6] sunxi: video: Add sun6i support

Hans de Goede
2014-11-14T16:54:46Z

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/video/sunxi_display.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)

diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index 74a92b5..1058771 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -39,6 +39,9 @@ sunxi_hdmi_hpd_detect(void)
CCM_HDMI_CTRL_PLL3);

/* Set ahb gating to pass */
+#ifdef CONFIG_MACH_SUN6I
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
+#endif
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);

/* Clock on */
@@ -56,6 +59,9 @@ sunxi_hdmi_hpd_detect(void)
clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
+#ifdef CONFIG_MACH_SUN6I
+ clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
+#endif
clock_set_pll3(0);

return 0;
@@ -74,6 +80,11 @@ sunxi_composer_init(void)
(struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
int i;

+#ifdef CONFIG_MACH_SUN6I
+ /* Reset off */
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
+#endif
+
/* Clocks on */
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
@@ -177,7 +188,11 @@ sunxi_lcdc_init(void)
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;

/* Reset off */
+#ifdef CONFIG_MACH_SUN6I
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
+#else
setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
+#endif

/* Clock on */
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
@@ -232,6 +247,19 @@ sunxi_lcdc_mode_set(struct fb_videomode *mode, int *clk_div, int *clk_double)
sunxi_lcdc_pll_set(mode->pixclock, clk_div, clk_double);
}

+#ifdef CONFIG_MACH_SUN6I
+static void
+sunxi_drc_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* On sun6i the drc must be clocked even when in pass-through mode */
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
+ clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
+}
+#endif
+
static void
sunxi_hdmi_mode_set(struct fb_videomode *mode, int clk_div, int clk_double)
{
@@ -283,6 +311,9 @@ sunxi_engines_init(void)
{
sunxi_composer_init();
sunxi_lcdc_init();
+#ifdef CONFIG_MACH_SUN6I
+ sunxi_drc_init();
+#endif
}

static void
--
2.1.0