From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Fri, 21 Nov 2014 13:30:10 +0100 Subject: [U-Boot] [PATCH] drivers: usb: fsl: Workaround for Erratum A004477 In-Reply-To: <1416570921-11444-1-git-send-email-nikhil.badola@freescale.com> References: <1416570921-11444-1-git-send-email-nikhil.badola@freescale.com> Message-ID: <20141121133010.6e83c03f@lilith> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hello Nikhil, On Fri, 21 Nov 2014 17:25:21 +0530, Nikhil Badola wrote: > Add a delay of 1 microsecond before issuing soft reset to the > controller to let ongoing ULPI transaction complete. > This prevents corruption of ULPI Function Control Register which > eventually prevents phy clock from entering to low power mode > > Signed-off-by: Nikhil Badola > --- > Depends on patch https://patchwork.ozlabs.org/patch/404879/ > > arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ > arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++ > drivers/usb/host/ehci-fsl.c | 10 ++++++++++ > include/fsl_usb.h | 29 +++++++++++++++++++++++++++++ > 4 files changed, 49 insertions(+) > > diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c > index fe3eb06..bc59352 100644 > --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c > +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c > @@ -298,6 +298,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) > if (has_erratum_a007798()) > puts("Work-around for Erratum A007798 enabled\n"); > #endif > +#ifdef CONFIG_SYS_FSL_ERRATUM_A004477 > + if (has_erratum_a004477()) > + puts("Work-around for Erratum A004477 enabled\n"); > +#endif > #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 > if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || > (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) > diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h > index 7860b40..fe9e9c1 100644 > --- a/arch/powerpc/include/asm/config_mpc85xx.h > +++ b/arch/powerpc/include/asm/config_mpc85xx.h > @@ -161,6 +161,7 @@ > #define CONFIG_SYS_FSL_ERRATUM_A004508 > #define CONFIG_SYS_FSL_ERRATUM_A007075 > #define CONFIG_SYS_FSL_ERRATUM_A006261 > +#define CONFIG_SYS_FSL_ERRATUM_A004477 > #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 > #define CONFIG_ESDHC_HC_BLK_ADDR > > @@ -292,6 +293,7 @@ > #define CONFIG_FSL_SATA_ERRATUM_A001 > #define CONFIG_SYS_FSL_ERRATUM_A004508 > #define CONFIG_SYS_FSL_ERRATUM_A005125 > +#define CONFIG_SYS_FSL_ERRATUM_A004477 > > #elif defined(CONFIG_P1023) > #define CONFIG_MAX_CPUS 2 > @@ -372,6 +374,7 @@ > #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 > #define CONFIG_SYS_FSL_ERRATUM_A004508 > #define CONFIG_SYS_FSL_ERRATUM_A005125 > +#define CONFIG_SYS_FSL_ERRATUM_A004477 > #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 > > #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ > @@ -589,6 +592,7 @@ > #define CONFIG_NAND_FSL_IFC > #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 > #define CONFIG_SYS_FSL_ERRATUM_A005125 > +#define CONFIG_SYS_FSL_ERRATUM_A004477 > #define CONFIG_ESDHC_HC_BLK_ADDR > > #elif defined(CONFIG_BSC9132) > @@ -613,6 +617,7 @@ > #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" > #define CONFIG_SYS_FSL_ERRATUM_A005125 > #define CONFIG_SYS_FSL_ERRATUM_A005434 > +#define CONFIG_SYS_FSL_ERRATUM_A004477 > #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 > #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 > #define CONFIG_ESDHC_HC_BLK_ADDR > @@ -712,6 +717,7 @@ > #define CONFIG_SYS_FSL_ERRATUM_A006475 > #define CONFIG_SYS_FSL_ERRATUM_A006384 > #define CONFIG_SYS_FSL_ERRATUM_A007212 > +#define CONFIG_SYS_FSL_ERRATUM_A004477 > #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 > #define CONFIG_SYS_FSL_SFP_VER_3_0 > > diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c > index 5d4288d..41ff1a7 100644 > --- a/drivers/usb/host/ehci-fsl.c > +++ b/drivers/usb/host/ehci-fsl.c > @@ -138,6 +138,16 @@ int ehci_hcd_init(int index, enum usb_init_type init, > if (has_erratum_a007798()) > set_txfifothresh(ehci, TXFIFOTHRESH); > > + if (has_erratum_a004477()) { > + /* > + * When reset is issued while any ULPI transaction is ongoing > + * then it may result to corruption of ULPI Function Control > + * Register which eventually causes phy clock to enter low > + * power mode which stops the clock. Thus delay is required > + * before reset to let ongoing ULPI transaction complete. Actually the erratum suggests checking transaction status before issuing a soft reset. Here, could the code do this check and wait for the transation to finish, rather than wait for an arbitrary duration? > + */ > + udelay(1); > + } > return 0; > } > > diff --git a/include/fsl_usb.h b/include/fsl_usb.h > index d251f5d..88d8a8b 100644 > --- a/include/fsl_usb.h > +++ b/include/fsl_usb.h > @@ -164,6 +164,30 @@ static inline bool has_erratum_a007792(void) > return false; > } > > +static inline bool has_erratum_a004477(void) > +{ > + u32 svr = get_svr(); > + u32 soc = SVR_SOC_VER(svr); > + > + switch (soc) { > + case SVR_P1010: > + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); > + case SVR_P1022: > + case SVR_9131: > + case SVR_9132: > + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); > + case SVR_P2020: > + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) || > + IS_SVR_REV(svr, 2, 1); > + case SVR_B4860: > + case SVR_B4420: > + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); > + case SVR_P4080: > + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); > + } > + > + return false; > +} > #else > static inline bool has_erratum_a006261(void) > { > @@ -184,5 +208,10 @@ static inline bool has_erratum_a007792(void) > { > return false; > } > + > +static inline bool has_erratum_a004477(void) > +{ > + return false; > +} > #endif > #endif /*_ASM_FSL_USB_H_ */ > -- > 1.7.11.7 > > > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot Amicalement, -- Albert.