* [U-Boot] [PATCH v3] bcm281xx: add support for "USB OTG clock"
@ 2014-12-09 19:40 Steve Rae
2014-12-09 21:21 ` Felipe Balbi
2014-12-30 2:26 ` [U-Boot] [U-Boot,v3] " Tom Rini
0 siblings, 2 replies; 3+ messages in thread
From: Steve Rae @ 2014-12-09 19:40 UTC (permalink / raw)
To: u-boot
enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
Signed-off-by: Steve Rae <srae@broadcom.com>
---
Changes in v3:
clean up return statement as per Michael Trimarchi <michael@amarulasolutions.com>
Changes in v2:
removed unrelated changes as per Felipe Balbi <balbi@ti.com>
arch/arm/cpu/armv7/bcm281xx/Makefile | 1 +
arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c | 16 ++++++++++++++++
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c | 27 +++++++++++++++++++++++++++
arch/arm/cpu/armv7/kona-common/clk-stubs.c | 5 +++++
arch/arm/include/asm/arch-bcm281xx/sysmap.h | 2 ++
arch/arm/include/asm/kona-common/clk.h | 1 +
6 files changed, 52 insertions(+)
create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile b/arch/arm/cpu/armv7/bcm281xx/Makefile
index bd867a2..f24aeb3 100644
--- a/arch/arm/cpu/armv7/bcm281xx/Makefile
+++ b/arch/arm/cpu/armv7/bcm281xx/Makefile
@@ -10,3 +10,4 @@ obj-y += clk-bcm281xx.o
obj-y += clk-sdio.o
obj-y += clk-bsc.o
obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y += clk-usb-otg.o
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
index d16b99f..7e25255 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
@@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
.gate = SW_ONLY_GATE(0x0360, 20, 4),
};
+static struct bus_clk_data usb_otg_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
static struct bus_clk_data sdio1_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
};
@@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
*/
/* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+ .clk = {
+ .name = "usb_otg_ahb_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = &usb_otg_ahb_data,
+};
+
static struct bus_clock sdio1_ahb_clk = {
.clk = {
.name = "sdio1_ahb_clk",
@@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
CLK_LK(bsc2),
CLK_LK(bsc3),
/* Bus clocks */
+ CLK_LK(usb_otg_ahb),
CLK_LK(sdio1_ahb),
CLK_LK(sdio2_ahb),
CLK_LK(sdio3_ahb),
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
new file mode 100644
index 0000000..1d7c5af
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+ char *ahbstr;
+
+ switch ((u32) base) {
+ case HSOTG_BASE_ADDR:
+ ahbstr = "usb_otg_ahb_clk";
+ break;
+ default:
+ printf("%s: base 0x%p not found\n", __func__, base);
+ return -EINVAL;
+ }
+
+ return clk_get_and_enable(ahbstr);
+}
diff --git a/arch/arm/cpu/armv7/kona-common/clk-stubs.c b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
index 338e0e4..fa10802 100644
--- a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
+++ b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
@@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
{
return 0;
}
+
+int __weak clk_usb_otg_enable(void *base)
+{
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
index 350e7f6..93ebf34 100644
--- a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
+++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
@@ -13,6 +13,8 @@
#define ESUB_CLK_BASE_ADDR 0x38000000
#define ESW_CONTRL_BASE_ADDR 0x38200000
#define GPIO2_BASE_ADDR 0x35003000
+#define HSOTG_BASE_ADDR 0x3f120000
+#define HSOTG_CTRL_BASE_ADDR 0x3f130000
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
#define PMU_BSC_BASE_ADDR 0x3500d000
diff --git a/arch/arm/include/asm/kona-common/clk.h b/arch/arm/include/asm/kona-common/clk.h
index 2c7e829..a5e2fd9 100644
--- a/arch/arm/include/asm/kona-common/clk.h
+++ b/arch/arm/include/asm/kona-common/clk.h
@@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
struct clk *clk_get_parent(struct clk *clk);
int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
#endif
--
1.8.5
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH v3] bcm281xx: add support for "USB OTG clock"
2014-12-09 19:40 [U-Boot] [PATCH v3] bcm281xx: add support for "USB OTG clock" Steve Rae
@ 2014-12-09 21:21 ` Felipe Balbi
2014-12-30 2:26 ` [U-Boot] [U-Boot,v3] " Tom Rini
1 sibling, 0 replies; 3+ messages in thread
From: Felipe Balbi @ 2014-12-09 21:21 UTC (permalink / raw)
To: u-boot
On Tue, Dec 09, 2014 at 11:40:11AM -0800, Steve Rae wrote:
> enable this clock with the following:
> clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
>
> Signed-off-by: Steve Rae <srae@broadcom.com>
my reviewed by remains :-)
Reviewed-by: Felipe Balbi <balbi@ti.com>
> ---
>
> Changes in v3:
> clean up return statement as per Michael Trimarchi <michael@amarulasolutions.com>
>
> Changes in v2:
> removed unrelated changes as per Felipe Balbi <balbi@ti.com>
>
> arch/arm/cpu/armv7/bcm281xx/Makefile | 1 +
> arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c | 16 ++++++++++++++++
> arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c | 27 +++++++++++++++++++++++++++
> arch/arm/cpu/armv7/kona-common/clk-stubs.c | 5 +++++
> arch/arm/include/asm/arch-bcm281xx/sysmap.h | 2 ++
> arch/arm/include/asm/kona-common/clk.h | 1 +
> 6 files changed, 52 insertions(+)
> create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
>
> diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile b/arch/arm/cpu/armv7/bcm281xx/Makefile
> index bd867a2..f24aeb3 100644
> --- a/arch/arm/cpu/armv7/bcm281xx/Makefile
> +++ b/arch/arm/cpu/armv7/bcm281xx/Makefile
> @@ -10,3 +10,4 @@ obj-y += clk-bcm281xx.o
> obj-y += clk-sdio.o
> obj-y += clk-bsc.o
> obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
> +obj-y += clk-usb-otg.o
> diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
> index d16b99f..7e25255 100644
> --- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
> +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
> @@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
> .gate = SW_ONLY_GATE(0x0360, 20, 4),
> };
>
> +static struct bus_clk_data usb_otg_ahb_data = {
> + .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
> +};
> +
> static struct bus_clk_data sdio1_ahb_data = {
> .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
> };
> @@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
> */
>
> /* KPM bus clocks */
> +static struct bus_clock usb_otg_ahb_clk = {
> + .clk = {
> + .name = "usb_otg_ahb_clk",
> + .parent = &kpm_ccu_clk.clk,
> + .ops = &bus_clk_ops,
> + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
> + },
> + .freq_tbl = master_ahb_freq_tbl,
> + .data = &usb_otg_ahb_data,
> +};
> +
> static struct bus_clock sdio1_ahb_clk = {
> .clk = {
> .name = "sdio1_ahb_clk",
> @@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
> CLK_LK(bsc2),
> CLK_LK(bsc3),
> /* Bus clocks */
> + CLK_LK(usb_otg_ahb),
> CLK_LK(sdio1_ahb),
> CLK_LK(sdio2_ahb),
> CLK_LK(sdio3_ahb),
> diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
> new file mode 100644
> index 0000000..1d7c5af
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
> @@ -0,0 +1,27 @@
> +/*
> + * Copyright 2014 Broadcom Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/errno.h>
> +#include <asm/arch/sysmap.h>
> +#include "clk-core.h"
> +
> +/* Enable appropriate clocks for the USB OTG port */
> +int clk_usb_otg_enable(void *base)
> +{
> + char *ahbstr;
> +
> + switch ((u32) base) {
> + case HSOTG_BASE_ADDR:
> + ahbstr = "usb_otg_ahb_clk";
> + break;
> + default:
> + printf("%s: base 0x%p not found\n", __func__, base);
> + return -EINVAL;
> + }
> +
> + return clk_get_and_enable(ahbstr);
> +}
> diff --git a/arch/arm/cpu/armv7/kona-common/clk-stubs.c b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
> index 338e0e4..fa10802 100644
> --- a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
> +++ b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
> @@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
> {
> return 0;
> }
> +
> +int __weak clk_usb_otg_enable(void *base)
> +{
> + return 0;
> +}
> diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
> index 350e7f6..93ebf34 100644
> --- a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
> +++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
> @@ -13,6 +13,8 @@
> #define ESUB_CLK_BASE_ADDR 0x38000000
> #define ESW_CONTRL_BASE_ADDR 0x38200000
> #define GPIO2_BASE_ADDR 0x35003000
> +#define HSOTG_BASE_ADDR 0x3f120000
> +#define HSOTG_CTRL_BASE_ADDR 0x3f130000
> #define KONA_MST_CLK_BASE_ADDR 0x3f001000
> #define KONA_SLV_CLK_BASE_ADDR 0x3e011000
> #define PMU_BSC_BASE_ADDR 0x3500d000
> diff --git a/arch/arm/include/asm/kona-common/clk.h b/arch/arm/include/asm/kona-common/clk.h
> index 2c7e829..a5e2fd9 100644
> --- a/arch/arm/include/asm/kona-common/clk.h
> +++ b/arch/arm/include/asm/kona-common/clk.h
> @@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
> struct clk *clk_get_parent(struct clk *clk);
> int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
> int clk_bsc_enable(void *base);
> +int clk_usb_otg_enable(void *base);
>
> #endif
> --
> 1.8.5
>
--
balbi
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^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot] [U-Boot,v3] bcm281xx: add support for "USB OTG clock"
2014-12-09 19:40 [U-Boot] [PATCH v3] bcm281xx: add support for "USB OTG clock" Steve Rae
2014-12-09 21:21 ` Felipe Balbi
@ 2014-12-30 2:26 ` Tom Rini
1 sibling, 0 replies; 3+ messages in thread
From: Tom Rini @ 2014-12-30 2:26 UTC (permalink / raw)
To: u-boot
On Tue, Dec 09, 2014 at 11:40:11AM -0800, Steve Rae wrote:
> enable this clock with the following:
> clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
>
> Signed-off-by: Steve Rae <srae@broadcom.com>
> Reviewed-by: Felipe Balbi <balbi@ti.com>
Applied to u-boot/master, thanks!
--
Tom
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2014-12-09 19:40 [U-Boot] [PATCH v3] bcm281xx: add support for "USB OTG clock" Steve Rae
2014-12-09 21:21 ` Felipe Balbi
2014-12-30 2:26 ` [U-Boot] [U-Boot,v3] " Tom Rini
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