[U-Boot] [PATCH 09/14] sun6i: Add k and m parameters to clock_set_pll5()

[Siarhei Siamashka <siarhei.siamashka@gmail.com>]

On Tue, 16 Dec 2014 21:31:34 +0100
Hans de Goede <hdegoede@redhat.com> wrote:

> The A23 (sun8i) requires different values for these then sun6i, so make them
> function parameters.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

What happens if A23 does not get these special k and m parameters, but
the 'clock_set_pll5' function picks some other values for them (with
the same resulting target clock speed)?

And if they are really required for A23, then why exposing them as the
function arguments instead of hiding this implementation detail inside
of the 'clock_set_pll5' function?

> ---
>  arch/arm/cpu/armv7/sunxi/clock_sun6i.c        | 4 +---
>  arch/arm/cpu/armv7/sunxi/dram_sun6i.c         | 2 +-
>  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 +-
>  3 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
> index 193e314..8ef19df 100644
> --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
> +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
> @@ -144,12 +144,10 @@ void clock_set_pll3(unsigned int clk)
>  	       &ccm->pll3_cfg);
>  }
>  
> -void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
> +void clock_set_pll5(unsigned int clk, int k, int m, bool sigma_delta_enable)
>  {
>  	struct sunxi_ccm_reg * const ccm =
>  		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> -	const int k = 2;
> -	const int m = 1;
>  
>  	if (sigma_delta_enable)
>  		writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
> diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
> index bc6428a..a8bbdfd 100644
> --- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
> +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
> @@ -46,7 +46,7 @@ static void mctl_sys_init(void)
>  		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>  	const int dram_clk_div = 2;
>  
> -	clock_set_pll5(DRAM_CLK * dram_clk_div, false);
> +	clock_set_pll5(DRAM_CLK * dram_clk_div, 2, 1, false);
>  
>  	clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
>  		CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index f807af3..7d61216 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -311,6 +311,6 @@ struct sunxi_ccm_reg {
>  #define CCM_DE_CTRL_PLL10		(5 << 24)
>  #define CCM_DE_CTRL_GATE		(1 << 31)
>  
> -void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
> +void clock_set_pll5(unsigned int clk, int k, int m, bool sigma_delta_enable);
>  
>  #endif /* _SUNXI_CLOCK_SUN6I_H */



-- 
Best regards,
Siarhei Siamashka