From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anatolij Gustschin Date: Sat, 10 Jan 2015 01:33:22 +0100 Subject: [U-Boot] [PATCH 6/8] video: ssd2828: Allow using 'pclk' as the PLL clock source In-Reply-To: <1420797676-22515-7-git-send-email-siarhei.siamashka@gmail.com> References: <1420797676-22515-1-git-send-email-siarhei.siamashka@gmail.com> <1420797676-22515-7-git-send-email-siarhei.siamashka@gmail.com> Message-ID: <20150110013322.12298a9d@crub> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Fri, 9 Jan 2015 12:01:14 +0200 Siarhei Siamashka wrote: > Instead of using the internal 'tx_clk' clock source, it is also > possible to use the pixel clock signal from the parallel LCD > interface ('pclk') as the reference clock for PLL. > > The 'tx_clk' clock speed may be different on different boards/devices > (the allowed range is 8MHz - 30MHz). Which is not very convenient, > especially considering the need to know the exact 'tx_clk' clock > speed. Which may be difficult to identify without having device > schematics and/or accurate documentation/sources every time. > > Using 'pclk' is free from all these problems. > > Signed-off-by: Siarhei Siamashka Acked-by: Anatolij Gustschin