From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Thu, 15 Jan 2015 00:44:01 +0100 Subject: [U-Boot] [PATCHv1 07/22] arm: socfpga: spl: enable sdram, timer and uart In-Reply-To: <1421253662-27222-8-git-send-email-dinguyen@opensource.altera.com> References: <1421253662-27222-1-git-send-email-dinguyen@opensource.altera.com> <1421253662-27222-8-git-send-email-dinguyen@opensource.altera.com> Message-ID: <201501150044.01645.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wednesday, January 14, 2015 at 05:40:47 PM, dinguyen at opensource.altera.com wrote: > From: Dinh Nguyen Commit message would not hurt here, but the Subject is already pretty clear about the purpose, so it's not a showstopper. It'd be nice to have though. > Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut > --- > arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/cpu/armv7/socfpga/spl.c > b/arch/arm/cpu/armv7/socfpga/spl.c index bd9f338..b123336 100644 > --- a/arch/arm/cpu/armv7/socfpga/spl.c > +++ b/arch/arm/cpu/armv7/socfpga/spl.c > @@ -145,6 +145,10 @@ void spl_board_init(void) > /* freeze all IO banks */ > sys_mgr_frzctrl_freeze_req(); > > + socfpga_sdram_enable(); > + socfpga_uart0_enable(); > + socfpga_osc1timer_enable(); > + > debug("Reconfigure Clock Manager\n"); > /* reconfigure the PLLs */ > cm_basic_init(&cm_default_cfg); Best regards, Marek Vasut