From mboxrd@z Thu Jan  1 00:00:00 1970
From: Albert ARIBAUD <albert.u.boot@aribaud.net>
Date: Sun, 1 Feb 2015 03:12:28 +0100
Subject: [U-Boot] [PATCH v2] arm/ls1021a: Add workaround for DDR erratum
 A008378
In-Reply-To: <1421268367-27117-1-git-send-email-yorksun@freescale.com>
References: <1421268367-27117-1-git-send-email-yorksun@freescale.com>
Message-ID: <20150201031228.7e1e229c@lilith>
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To: u-boot@lists.denx.de

Hello York Sun,

On Wed, 14 Jan 2015 12:46:07 -0800, York Sun <yorksun@freescale.com>
wrote:
> Internal memory controller counters can reach a bad state after
> training in DDR4 mode if accumulated ECC or DBI mode is eanbled.

typo: eanbled -> enabled.

Amicalement,
-- 
Albert.