From mboxrd@z Thu Jan 1 00:00:00 1970 From: Curt Brune Date: Thu, 12 Feb 2015 21:35:12 -0800 Subject: [U-Boot] MPC8541 / MPC8555E: DDR_SDRAM_CLK_CNLT[SS_EN] handling Message-ID: <20150213053512.GL4740@cumulusnetworks.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hello, I am curious about the setting of the SS_EN bit in the DDR_SDRAM_CLK_CNLT register: Source synchronous enable. This bit field must be set during initialization. See Section 9.6.1, ?DDR SDRAM Initialization Sequence,? for details. 0 - Reserved 1 - The address and command are sent to the DDR SDRAMs source synchronously. The MPC8555E reference manual and this app note are pretty clear that this bit should be set: http://cache.freescale.com/files/32bit/doc/app_note/AN2805.pdf (page 17) set_ddr_sdram_clk_cntl() in u-boot/drivers/ddr/fsl/ctrl_regs.c has this: clk_adjust = popts->clk_adjust; ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; There is no accounting for the SS_EN bit on 8541/8555E. I would have expected to see an #ifdef for the MPC8555 that sets the SS_EN bit. I know 8541 has been around forever and is working fine. I am just trying to find some back ground information on this setting. Searching the old mailing lists did not turn up anything useful. Any insight is appreciated. Cheers, Curt