From: Tom Rini <trini@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [U-Boot, 2/3] ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
Date: Tue, 17 Feb 2015 15:24:25 -0500 [thread overview]
Message-ID: <20150217202425.GV11752@bill-the-cat> (raw)
In-Reply-To: <1424061957-7637-3-git-send-email-lokeshvutla@ti.com>
On Mon, Feb 16, 2015 at 10:15:56AM +0530, Lokesh Vutla wrote:
> The value in SDRAM_REF_CTRL controls the delay time between
> the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
> (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
> should be written with a value corresponding to 500us delay before
> starting DDR initialization sequence, and configure proper
> value at the end of sequence.
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Applied to u-boot/master, thanks!
--
Tom
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next prev parent reply other threads:[~2015-02-17 20:24 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-16 4:45 [U-Boot] [PATCH 0/3] ARM: DRA7: DDR3: Update timings and leveling parameters Lokesh Vutla
2015-02-16 4:45 ` [U-Boot] [PATCH 1/3] ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock Lokesh Vutla
2015-02-17 20:24 ` [U-Boot] [U-Boot, " Tom Rini
2015-02-17 20:24 ` Tom Rini
2015-02-16 4:45 ` [U-Boot] [PATCH 2/3] ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value Lokesh Vutla
2015-02-17 20:24 ` Tom Rini [this message]
2015-02-16 4:45 ` [U-Boot] [PATCH 3/3] ARM: DRA7-evm: DDR3: Update leveling values Lokesh Vutla
2015-02-17 20:24 ` [U-Boot] [U-Boot, " Tom Rini
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