From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Tue, 17 Feb 2015 15:24:25 -0500 Subject: [U-Boot] [U-Boot, 2/3] ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value In-Reply-To: <1424061957-7637-3-git-send-email-lokeshvutla@ti.com> References: <1424061957-7637-3-git-send-email-lokeshvutla@ti.com> Message-ID: <20150217202425.GV11752@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, Feb 16, 2015 at 10:15:56AM +0530, Lokesh Vutla wrote: > The value in SDRAM_REF_CTRL controls the delay time between > the initial rising edge of DDR_RESETn to rising edge of DDR_CKE > (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL > should be written with a value corresponding to 500us delay before > starting DDR initialization sequence, and configure proper > value at the end of sequence. > > Signed-off-by: Lokesh Vutla Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: