* [U-Boot] [PATCH 1/3] ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock
2015-02-16 4:45 [U-Boot] [PATCH 0/3] ARM: DRA7: DDR3: Update timings and leveling parameters Lokesh Vutla
@ 2015-02-16 4:45 ` Lokesh Vutla
2015-02-17 20:24 ` [U-Boot] [U-Boot, " Tom Rini
2015-02-17 20:24 ` Tom Rini
2015-02-16 4:45 ` [U-Boot] [PATCH 2/3] ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value Lokesh Vutla
2015-02-16 4:45 ` [U-Boot] [PATCH 3/3] ARM: DRA7-evm: DDR3: Update leveling values Lokesh Vutla
2 siblings, 2 replies; 8+ messages in thread
From: Lokesh Vutla @ 2015-02-16 4:45 UTC (permalink / raw)
To: u-boot
From: Angela Stegmaier <angelabaker@ti.com>
DDR3 timing and latency paramenters were not configured
correctly for 666MHz. Fixing the timing and latency values
according to Data sheet.
This fixes the random crashes seen on DRA72-evm.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm/cpu/armv7/omap5/sdram.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7d8cec0..e5456ff 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -186,18 +186,18 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
};
const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
- .sdram_config_init = 0x61851AB2,
- .sdram_config = 0x61851AB2,
+ .sdram_config_init = 0x61862B32,
+ .sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x027F88A8,
+ .ref_ctrl = 0x0000144A,
+ .sdram_tim1 = 0xD113781C,
+ .sdram_tim2 = 0x308F7FE3,
+ .sdram_tim3 = 0x009F86A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400A,
- .emif_ddr_phy_ctlr_1 = 0x0024400A,
+ .emif_ddr_phy_ctlr_1_init = 0x0E24400D,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
.emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [U-Boot] [U-Boot, 1/3] ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock
2015-02-16 4:45 ` [U-Boot] [PATCH 1/3] ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock Lokesh Vutla
@ 2015-02-17 20:24 ` Tom Rini
2015-02-17 20:24 ` Tom Rini
1 sibling, 0 replies; 8+ messages in thread
From: Tom Rini @ 2015-02-17 20:24 UTC (permalink / raw)
To: u-boot
On Mon, Feb 16, 2015 at 10:15:55AM +0530, Lokesh Vutla wrote:
> From: Angela Stegmaier <angelabaker@ti.com>
>
> DDR3 timing and latency paramenters were not configured
> correctly for 666MHz. Fixing the timing and latency values
> according to Data sheet.
> This fixes the random crashes seen on DRA72-evm.
>
> Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [U-Boot, 1/3] ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock
2015-02-16 4:45 ` [U-Boot] [PATCH 1/3] ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock Lokesh Vutla
2015-02-17 20:24 ` [U-Boot] [U-Boot, " Tom Rini
@ 2015-02-17 20:24 ` Tom Rini
1 sibling, 0 replies; 8+ messages in thread
From: Tom Rini @ 2015-02-17 20:24 UTC (permalink / raw)
To: u-boot
On Mon, Feb 16, 2015 at 10:15:55AM +0530, Lokesh Vutla wrote:
> From: Angela Stegmaier <angelabaker@ti.com>
>
> DDR3 timing and latency paramenters were not configured
> correctly for 666MHz. Fixing the timing and latency values
> according to Data sheet.
> This fixes the random crashes seen on DRA72-evm.
>
> Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/3] ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
2015-02-16 4:45 [U-Boot] [PATCH 0/3] ARM: DRA7: DDR3: Update timings and leveling parameters Lokesh Vutla
2015-02-16 4:45 ` [U-Boot] [PATCH 1/3] ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock Lokesh Vutla
@ 2015-02-16 4:45 ` Lokesh Vutla
2015-02-17 20:24 ` [U-Boot] [U-Boot, " Tom Rini
2015-02-16 4:45 ` [U-Boot] [PATCH 3/3] ARM: DRA7-evm: DDR3: Update leveling values Lokesh Vutla
2 siblings, 1 reply; 8+ messages in thread
From: Lokesh Vutla @ 2015-02-16 4:45 UTC (permalink / raw)
To: u-boot
The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 4 +++-
arch/arm/cpu/armv7/omap5/sdram.c | 9 ++++++---
arch/arm/include/asm/emif.h | 1 +
board/ti/beagle_x15/board.c | 6 ++++--
4 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index e601ba1..c01a98f 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -252,6 +252,8 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
* and RL =7. As the default values of the Mode Registers are not
@@ -265,7 +267,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
/*
@@ -274,6 +275,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
*/
if (is_dra7xx()) {
do_ext_phy_settings(base, regs);
+ writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
} else {
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index e5456ff..61e9aef 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -141,7 +141,8 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
@@ -165,7 +166,8 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
@@ -189,7 +191,8 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000144A,
+ .ref_ctrl = 0x0000493E,
+ .ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD113781C,
.sdram_tim2 = 0x308F7FE3,
.sdram_tim3 = 0x009F86A8,
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 2fe5776..5a7a812 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1122,6 +1122,7 @@ struct emif_regs {
u32 sdram_config;
u32 sdram_config2;
u32 ref_ctrl;
+ u32 ref_ctrl_final;
u32 sdram_tim1;
u32 sdram_tim2;
u32 sdram_tim3;
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
index db96e34..3a7e04d 100644
--- a/board/ti/beagle_x15/board.c
+++ b/board/ti/beagle_x15/board.c
@@ -47,7 +47,8 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x00000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
@@ -103,7 +104,8 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x00000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [U-Boot] [PATCH 3/3] ARM: DRA7-evm: DDR3: Update leveling values
2015-02-16 4:45 [U-Boot] [PATCH 0/3] ARM: DRA7: DDR3: Update timings and leveling parameters Lokesh Vutla
2015-02-16 4:45 ` [U-Boot] [PATCH 1/3] ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock Lokesh Vutla
2015-02-16 4:45 ` [U-Boot] [PATCH 2/3] ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value Lokesh Vutla
@ 2015-02-16 4:45 ` Lokesh Vutla
2015-02-17 20:24 ` [U-Boot] [U-Boot, " Tom Rini
2 siblings, 1 reply; 8+ messages in thread
From: Lokesh Vutla @ 2015-02-16 4:45 UTC (permalink / raw)
To: u-boot
Update the software leveling parameters.
This fixes the random crash seen on DRA7-evm.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm/cpu/armv7/omap5/sdram.c | 60 ++++++++++++++++++++--------------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 61e9aef..5f8daa1 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -152,10 +152,10 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@@ -177,10 +177,10 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@@ -423,22 +423,22 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
- 0x00BB00BB,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
+ 0x00980098,
+ 0x00340034,
+ 0x00350035,
+ 0x00340034,
+ 0x00310031,
+ 0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
+ 0x00480048,
+ 0x004A004A,
+ 0x00520052,
+ 0x00550055,
+ 0x00500050,
0x00000000,
0x00600020,
0x40010080,
@@ -452,22 +452,22 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
- 0x00BB00BB,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
+ 0x00980098,
+ 0x00330033,
+ 0x00330033,
+ 0x002F002F,
+ 0x00320032,
+ 0x00310031,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
+ 0x00520052,
+ 0x00520052,
+ 0x00470047,
+ 0x00490049,
+ 0x00500050,
0x00000000,
0x00600020,
0x40010080,
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread