[U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry

[U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry

[Marek Vasut]

Add DWC SPI controller Kconfig entry.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
---
 drivers/spi/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7ae2727..c0b2570 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -10,3 +10,9 @@ config DM_SPI
 	  as 'parent data' to every slave on each bus. Slaves
 	  typically use driver-private data instead of extending the
 	  spi_slave structure.
+
+config DESIGNWARE_SPI
+	bool "Designware SPI driver"
+	depends on DM_SPI
+	help
+	  Enable the Designware SPI driver.
-- 
2.1.3

[U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry

[Marek Vasut]

Add Cadence QSPI controller Kconfig entry.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
---
 drivers/spi/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c0b2570..eaf31ed 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -16,3 +16,9 @@ config DESIGNWARE_SPI
 	depends on DM_SPI
 	help
 	  Enable the Designware SPI driver.
+
+config CADENCE_QSPI
+	bool "Cadence QSPI driver"
+	depends on DM_SPI
+	help
+	  Enable the Cadence QSPI driver.
-- 
2.1.3

[U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry

[Stefan Roese]

On 04.03.2015 23:22, Marek Vasut wrote:
> Add Cadence QSPI controller Kconfig entry.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <clsee@opensource.altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Vince Bridgers <vbridger@opensource.altera.com>

Acked-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

[U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry

[Simon Glass]

Hi Marek,

On 4 March 2015 at 15:22, Marek Vasut <marex@denx.de> wrote:
> Add Cadence QSPI controller Kconfig entry.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <clsee@opensource.altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Vince Bridgers <vbridger@opensource.altera.com>
> ---
>  drivers/spi/Kconfig | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index c0b2570..eaf31ed 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -16,3 +16,9 @@ config DESIGNWARE_SPI
>         depends on DM_SPI
>         help
>           Enable the Designware SPI driver.
> +
> +config CADENCE_QSPI
> +       bool "Cadence QSPI driver"
> +       depends on DM_SPI
> +       help
> +         Enable the Cadence QSPI driver.

Can we get a bit more detail here? What does QSPI mean? What features
does it support?

Regards,
Simon

[U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry

[Marek Vasut]

On Thursday, March 05, 2015 at 04:58:19 PM, Simon Glass wrote:
> Hi Marek,
> 
> On 4 March 2015 at 15:22, Marek Vasut <marex@denx.de> wrote:
> > Add Cadence QSPI controller Kconfig entry.
> > 
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Chin Liang See <clsee@opensource.altera.com>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> > Cc: Pavel Machek <pavel@denx.de>
> > Cc: Simon Glass <sjg@chromium.org>
> > Cc: Stefan Roese <sr@denx.de>
> > Cc: Tom Rini <trini@konsulko.com>
> > Cc: Vince Bridgers <vbridger@opensource.altera.com>
> > ---
> > 
> >  drivers/spi/Kconfig | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > index c0b2570..eaf31ed 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -16,3 +16,9 @@ config DESIGNWARE_SPI
> > 
> >         depends on DM_SPI
> >         help
> >         
> >           Enable the Designware SPI driver.
> > 
> > +
> > +config CADENCE_QSPI
> > +       bool "Cadence QSPI driver"
> > +       depends on DM_SPI
> > +       help
> > +         Enable the Cadence QSPI driver.
> 
> Can we get a bit more detail here? What does QSPI mean? What features
> does it support?

Stefan ? ;-)

Best regards,
Marek Vasut

[U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry

[Stefan Roese]

On 05.03.2015 17:14, Marek Vasut wrote:
>>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>>> index c0b2570..eaf31ed 100644
>>> --- a/drivers/spi/Kconfig
>>> +++ b/drivers/spi/Kconfig
>>> @@ -16,3 +16,9 @@ config DESIGNWARE_SPI
>>>
>>>          depends on DM_SPI
>>>          help
>>>
>>>            Enable the Designware SPI driver.
>>>
>>> +
>>> +config CADENCE_QSPI
>>> +       bool "Cadence QSPI driver"
>>> +       depends on DM_SPI
>>> +       help
>>> +         Enable the Cadence QSPI driver.
>>
>> Can we get a bit more detail here? What does QSPI mean? What features
>> does it support?
>
> Stefan ? ;-)

Its the IP core from Cadence supporting SPI NOR flash and is present on 
the Altera SoCFPGA. Enabling access to such SPI NOR flash devices. QSPI 
stands for Quad-SPI and refers to the optional use of up to 4 data lines 
for flash access.

So perhaps something like this:

+
+config CADENCE_QSPI
+	bool "Cadence QSPI driver"
+	depends on DM_SPI
+	help
+	  Enable the Cadence QSPI driver. This driver can be used to +	 
access the SPI NOR flash on platforms embedding this
+	  Cadence IP core (like the Altera SoCFPGA). QSPI stands for
+	  Quad-SPI and refers to the optional use of up to 4 data lines
+	  for flash access.

HTP.

Thanks,
Stefan

[U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry

[Tom Rini]

On Thu, Mar 05, 2015 at 05:30:26PM +0100, Stefan Roese wrote:
> On 05.03.2015 17:14, Marek Vasut wrote:
> >>>diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> >>>index c0b2570..eaf31ed 100644
> >>>--- a/drivers/spi/Kconfig
> >>>+++ b/drivers/spi/Kconfig
> >>>@@ -16,3 +16,9 @@ config DESIGNWARE_SPI
> >>>
> >>>         depends on DM_SPI
> >>>         help
> >>>
> >>>           Enable the Designware SPI driver.
> >>>
> >>>+
> >>>+config CADENCE_QSPI
> >>>+       bool "Cadence QSPI driver"
> >>>+       depends on DM_SPI
> >>>+       help
> >>>+         Enable the Cadence QSPI driver.
> >>
> >>Can we get a bit more detail here? What does QSPI mean? What features
> >>does it support?
> >
> >Stefan ? ;-)
> 
> Its the IP core from Cadence supporting SPI NOR flash and is present
> on the Altera SoCFPGA. Enabling access to such SPI NOR flash
> devices. QSPI stands for Quad-SPI and refers to the optional use of
> up to 4 data lines for flash access.
> 
> So perhaps something like this:
> 
> +
> +config CADENCE_QSPI
> +	bool "Cadence QSPI driver"
> +	depends on DM_SPI
> +	help
> +	  Enable the Cadence QSPI driver. This driver can be used to +	
> access the SPI NOR flash on platforms embedding this
> +	  Cadence IP core (like the Altera SoCFPGA). QSPI stands for
> +	  Quad-SPI and refers to the optional use of up to 4 data lines
> +	  for flash access.

Please don't mention platforms in the help for what I think of as
IP-block-vendor drivers.  The Cadence QSPI block will be reused by
others and I can see someone "needing" to patch the help text.  How
about:
	  Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to
	  access the SPI NOR flash on platforms embedding this
	  Cadence IP core.

-- 
Tom
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[U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry

[Stefan Roese]

On 05.03.2015 17:39, Tom Rini wrote:
> On Thu, Mar 05, 2015 at 05:30:26PM +0100, Stefan Roese wrote:
>> On 05.03.2015 17:14, Marek Vasut wrote:
>>>>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>>>>> index c0b2570..eaf31ed 100644
>>>>> --- a/drivers/spi/Kconfig
>>>>> +++ b/drivers/spi/Kconfig
>>>>> @@ -16,3 +16,9 @@ config DESIGNWARE_SPI
>>>>>
>>>>>          depends on DM_SPI
>>>>>          help
>>>>>
>>>>>            Enable the Designware SPI driver.
>>>>>
>>>>> +
>>>>> +config CADENCE_QSPI
>>>>> +       bool "Cadence QSPI driver"
>>>>> +       depends on DM_SPI
>>>>> +       help
>>>>> +         Enable the Cadence QSPI driver.
>>>>
>>>> Can we get a bit more detail here? What does QSPI mean? What features
>>>> does it support?
>>>
>>> Stefan ? ;-)
>>
>> Its the IP core from Cadence supporting SPI NOR flash and is present
>> on the Altera SoCFPGA. Enabling access to such SPI NOR flash
>> devices. QSPI stands for Quad-SPI and refers to the optional use of
>> up to 4 data lines for flash access.
>>
>> So perhaps something like this:
>>
>> +
>> +config CADENCE_QSPI
>> +	bool "Cadence QSPI driver"
>> +	depends on DM_SPI
>> +	help
>> +	  Enable the Cadence QSPI driver. This driver can be used to +	
>> access the SPI NOR flash on platforms embedding this
>> +	  Cadence IP core (like the Altera SoCFPGA). QSPI stands for
>> +	  Quad-SPI and refers to the optional use of up to 4 data lines
>> +	  for flash access.
>
> Please don't mention platforms in the help for what I think of as
> IP-block-vendor drivers.  The Cadence QSPI block will be reused by
> others and I can see someone "needing" to patch the help text.  How
> about:
> 	  Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to
> 	  access the SPI NOR flash on platforms embedding this
> 	  Cadence IP core.

Even better.

Thanks,
Stefan

[U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry

[Marek Vasut]

On Thursday, March 05, 2015 at 05:47:01 PM, Stefan Roese wrote:
[...]
> > Please don't mention platforms in the help for what I think of as
> > IP-block-vendor drivers.  The Cadence QSPI block will be reused by
> > others and I can see someone "needing" to patch the help text.  How
> > 
> > about:
> > 	  Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to
> > 	  access the SPI NOR flash on platforms embedding this
> > 	  Cadence IP core.
> 
> Even better.

Thanks

Best regards,
Marek Vasut

[U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry

[Stefan Roese]

On 04.03.2015 23:22, Marek Vasut wrote:
> Add DWC SPI controller Kconfig entry.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <clsee@opensource.altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Vince Bridgers <vbridger@opensource.altera.com>

Acked-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

[U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry

[Pavel Machek]

On Wed 2015-03-04 23:22:50, Marek Vasut wrote:
> Add DWC SPI controller Kconfig entry.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <clsee@opensource.altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

Acked-by: Pavel Machek <pavel@denx.de>

(For both patches in the series).


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry

[Simon Glass]

Hi,

On 4 March 2015 at 15:22, Marek Vasut <marex@denx.de> wrote:
> Add DWC SPI controller Kconfig entry.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <clsee@opensource.altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Vince Bridgers <vbridger@opensource.altera.com>
> ---
>  drivers/spi/Kconfig | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 7ae2727..c0b2570 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -10,3 +10,9 @@ config DM_SPI
>           as 'parent data' to every slave on each bus. Slaves
>           typically use driver-private data instead of extending the
>           spi_slave structure.
> +
> +config DESIGNWARE_SPI
> +       bool "Designware SPI driver"
> +       depends on DM_SPI
> +       help
> +         Enable the Designware SPI driver.

At least for driver model I'd like to have a nice long help message.

Regards,
Simon