From: Tom Rini <trini@konsulko.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [U-Boot, v2] mtd: nand: omap_gpmc: Make ready/busy pins configurable
Date: Fri, 6 Mar 2015 10:47:02 -0500 [thread overview]
Message-ID: <20150306154702.GX25373@bill-the-cat> (raw)
In-Reply-To: <1424189317-29655-1-git-send-email-sojkam1@fel.cvut.cz>
On Tue, Feb 17, 2015 at 05:08:37PM +0100, Michal Sojka wrote:
> From: Michal Sojka <sojka@merica.cz>
>
> Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of
> WAIT0 pin for determining whether the NAND is ready or not. This only
> works if all NAND chips are connected to WAIT0. If some chips are
> connected to the other available pin WAIT1, nand_wait() does not really
> wait and prints a WARN_ON message.
>
> This patch allows the board to provide configuration of which chip is
> connected to which WAITx signal. For example, one can define in
> include/configs/foo.h:
>
> #define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1
>
> This would mean that chips using to CS0 and 1 are connected to WAIT0 and
> chips with CS2 and 3 are connected to WAIT1.
>
> Signed-off-by: Michal Sojka <sojka@merica.cz>
> Acked-by: Stefan Roese <sr@denx.de>
> Tested-by: Michal Vok?? <michal.vokac@comap.cz>
>
> Cc: Tom Rini <trini@ti.com>
Applied to u-boot/master, thanks!
--
Tom
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prev parent reply other threads:[~2015-03-06 15:47 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-17 16:08 [U-Boot] [PATCH v2] mtd: nand: omap_gpmc: Make ready/busy pins configurable sojkam1 at fel.cvut.cz
2015-03-06 15:47 ` Tom Rini [this message]
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