From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Fri, 3 Apr 2015 03:54:43 +0200
Subject: [U-Boot] [PATCHv3 15/17] arm: socfpga: spl: update pll_config
	for dev kit
In-Reply-To: <1427752878-18426-16-git-send-email-dinguyen@opensource.altera.com>
References: <1427752878-18426-1-git-send-email-dinguyen@opensource.altera.com>
 <1427752878-18426-16-git-send-email-dinguyen@opensource.altera.com>
Message-ID: <201504030354.44106.marex@denx.de>
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To: u-boot@lists.denx.de

On Tuesday, March 31, 2015 at 12:01:16 AM, dinguyen at opensource.altera.com wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> This sets the CPU clocks to 925MHz and DDR to 400MHz, and the correct
> CONFIG_HPS_MAINPLLGRP_VCO_NUMER should be 79.

Didn't various CV SX run at 800MHz only ? I think only some of them ran
at 925MHz, not all of them.

> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> Reviewed-by: Marek Vasut <marex@denx.de>

[...]

Best regards,
Marek Vasut