[U-Boot] [PATCHv3 15/17] arm: socfpga: spl: update pll_config for dev kit

dinguyen at opensource.altera.com
2015-03-30T22:01:16Z

From: Dinh Nguyen <dinguyen@opensource.altera.com>

This sets the CPU clocks to 925MHz and DDR to 400MHz, and the correct
CONFIG_HPS_MAINPLLGRP_VCO_NUMER should be 79.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Reviewed-by: Marek Vasut <marex@denx.de>
---
board/altera/socfpga/pll_config.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h
index 8130fa4..90849b1 100644
--- a/board/altera/socfpga/pll_config.h
+++ b/board/altera/socfpga/pll_config.h
@@ -12,7 +12,7 @@
/* PLL configuration data */
/* Main PLL */
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (73)
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
@@ -36,7 +36,7 @@

/* Peripheral PLL */
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
/*
* To tell where is the VCOs source:
* 0 = EOSC1
--
2.2.1