[U-Boot] [PATCH 1/2] armv8: caches: Disable dcache after flush

[Mark Rutland <mark.rutland@arm.com>]

On Wed, Apr 15, 2015 at 12:33:00PM +0100, Michal Simek wrote:
> From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
> 
> Always disable dcache after the flush operation
> The following sequence is advisable while disabling d-cache:
> 1. disable_dcache() - flushes and disables d-cache
> 2. invalidate_dcache_all() - invalid any entry that came to the cache
>    in the short period after the cache was flushed but before the
>    cache got disabled

For reasons I have described previously (see [1,2,3]), this is unsafe.
The first cache flush may achieve nothing.

If you need data out at the PoC before disabling the cache, then you
should first use maintenance by VA to push that data out.

Thanks,
Mark.

[1] http://lists.denx.de/pipermail/u-boot/2015-February/204403.html
[2] http://lists.denx.de/pipermail/u-boot/2015-February/204407.html
[3] http://lists.denx.de/pipermail/u-boot/2015-February/204702.html

> 
> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> 
>  arch/arm/cpu/armv8/cache_v8.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index c5ec5297cd39..2a0492fbef52 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -128,10 +128,10 @@ void dcache_disable(void)
>  	if (!(sctlr & CR_C))
>  		return;
>  
> -	set_sctlr(sctlr & ~(CR_C|CR_M));
> -
>  	flush_dcache_all();
>  	__asm_invalidate_tlb_all();
> +
> +	set_sctlr(sctlr & ~(CR_C|CR_M));
>  }
>  
>  int dcache_status(void)
> -- 
> 2.3.5
> 
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