From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Thu, 16 Apr 2015 08:24:02 +0200 Subject: [U-Boot] [PATCHv3 15/17] arm: socfpga: spl: update pll_config for dev kit In-Reply-To: <552ECEC7.3020608@opensource.altera.com> References: <1427752878-18426-1-git-send-email-dinguyen@opensource.altera.com> <201504030354.44106.marex@denx.de> <552ECEC7.3020608@opensource.altera.com> Message-ID: <201504160824.02261.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wednesday, April 15, 2015 at 10:49:11 PM, Dinh Nguyen wrote: > On 04/02/2015 08:54 PM, Marek Vasut wrote: > > On Tuesday, March 31, 2015 at 12:01:16 AM, dinguyen at opensource.altera.com wrote: > >> From: Dinh Nguyen > >> > >> This sets the CPU clocks to 925MHz and DDR to 400MHz, and the correct > >> CONFIG_HPS_MAINPLLGRP_VCO_NUMER should be 79. > > > > Didn't various CV SX run at 800MHz only ? I think only some of them ran > > at 925MHz, not all of them. > > Ah yes, I think I'm lucky to have a 925MHz devkit on my desk. But I > think CONFIG_HPS_MAINPLLGRP_VCO_NUMER should be 79, as I cannot get a > correct baudrate without it. Yep, you and me are both lucky. The AV is also 925MHz part. I have some SoCrates and MCV SoMs which are 800 MHz parts, so I'd like to keep those parts operational, but I think I'll just have to figure something out on a per-board basis. I'll check the subsequent patch and see if I can pick it up now. Thanks! Best regards, Marek Vasut