[U-Boot] [PATCH v6 05/26] tegra: pwm: Allow the clock rate to be left as is

Simon Glass
2015-04-15T03:03:23Z

When enabling a PWM, allow the existing clock rate and source to stand
unchanged.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

arch/arm/include/asm/arch-tegra/pwm.h | 2 +-
arch/arm/mach-tegra/pwm.c | 5 ++++-
2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra/pwm.h b/arch/arm/include/asm/arch-tegra/pwm.h
index 8e7397d..92dced4 100644
--- a/arch/arm/include/asm/arch-tegra/pwm.h
+++ b/arch/arm/include/asm/arch-tegra/pwm.h
@@ -31,7 +31,7 @@ struct pwm_ctlr {
* Program the PWM with the given parameters.
*
* @param channel PWM channel to update
- * @param rate Clock rate to use for PWM
+ * @param rate Clock rate to use for PWM, or 0 to leave alone
* @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high,
* n = n/256 pulse high
* @param freq_divider frequency divider value (1 to use rate as is)
diff --git a/arch/arm/mach-tegra/pwm.c b/arch/arm/mach-tegra/pwm.c
index 8664200..1c38fc1 100644
--- a/arch/arm/mach-tegra/pwm.c
+++ b/arch/arm/mach-tegra/pwm.c
@@ -24,7 +24,10 @@ void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider)
assert(channel < PWM_NUM_CHANNELS);

/* TODO: Can we use clock_adjust_periph_pll_div() here? */
- clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate);
+ if (rate) {
+ clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ,
+ rate);
+ }

reg = PWM_ENABLE_MASK;
reg |= pulse_width << PWM_WIDTH_SHIFT;
--
2.2.0.rc0.207.ga3a616c