[U-Boot] [PATCH 2/4][v2]drivers:usb:fsl: Add XHCI driver support

[Marek Vasut <marex@denx.de>]

On Thursday, April 23, 2015 at 07:02:54 PM, Ramneek Mehresh wrote:
> Add xhci driver support for all FSL socs
> 
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

Next time, please follow

http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions

> ---
>  arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |   6 ++
>  drivers/usb/host/Makefile                         |   1 +
>  drivers/usb/host/xhci-fsl.c                       | 107
> ++++++++++++++++++++++ include/linux/usb/xhci-fsl.h                      |
>  54 +++++++++++ 4 files changed, 168 insertions(+)
>  create mode 100644 drivers/usb/host/xhci-fsl.c
>  create mode 100644 include/linux/usb/xhci-fsl.h
> 
> diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
> b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 3a64afc..9c1f1ce
> 100644
> --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
> +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
> @@ -538,4 +538,10 @@ struct ccsr_cci400 {
>  	} pcounter[4];			/* Performance Counter */
>  	u8 res_e004[0x10000 - 0xe004];
>  };
> +
> +/* USB-XHCI */
> +#define FSL_XHCI_BASE 0x3100000
> +#define FSL_OCP1_SCP_BASE 0x4a084c00
> +#define FSL_OTG_WRAPPER_BASE 0x4A020000
> +
>  #endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */

This file looks like a dumpster . Maybe it's about time for someone
in Freescale to clean that mess up. I don't want you to fix it before
this patchset is applied, but certainly this could use some fixing.

[...]

> +static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
> +{
> +	/* Currently fsl socs do not support PHY shutdown from
> +	 * sw. But this support may be added in future socs.
> +	 */

Multiline comment ;-)

> +	return 0;
> +}

[...]

> diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
> new file mode 100644
> index 0000000..8eaab2c
> --- /dev/null
> +++ b/include/linux/usb/xhci-fsl.h
> @@ -0,0 +1,54 @@
> +/*
> + * Copyright 2015 Freescale Semiconductor, Inc.
> + *
> + * FSL USB HOST xHCI Controller
> + *
> + * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef _ASM_ARCH_XHCI_FSL_H_
> +#define _ASM_ARCH_XHCI_FSL_H_
> +
> +/* Default to the FSL XHCI defines */
> +#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
> +#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
> +#define USB3_PHY_PARTIAL_RX_POWERON     BIT(6)
> +#define USB3_PHY_RX_POWERON		BIT(14)
> +#define USB3_PHY_TX_POWERON		BIT(15)
> +#define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON | 
USB3_PHY_TX_POWERON)
> +#define USB3_PWRCTL_CLK_CMD_SHIFT   14
> +#define USB3_PWRCTL_CLK_FREQ_SHIFT	22

How much of this is actually DWC3 stuff please ? Or are all
these bits really FSL-specific ?