From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT
Date: Wed, 20 May 2015 13:06:21 +0200 [thread overview]
Message-ID: <201505201306.21556.marex@denx.de> (raw)
In-Reply-To: <1432088928-7414-1-git-send-email-Peng.Fan@freescale.com>
On Wednesday, May 20, 2015 at 04:28:48 AM, Peng Fan wrote:
> We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
> that socs' cache line size is 32 bytes.
> If on chips whose cache line size is 64 bytes, error occurs:
Which chips are those?
> NAND: ERROR: v7_dcache_inval_range - start address is not aligned -
> 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned -
> 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned -
> 0xbdf1d1a0 "
> Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
> CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Best regards,
Marek Vasut
next prev parent reply other threads:[~2015-05-20 11:06 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-20 2:28 [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT Peng Fan
2015-05-20 11:06 ` Marek Vasut [this message]
2015-05-21 1:16 ` Peng Fan
2015-05-21 1:26 ` Marek Vasut
2015-05-25 13:08 ` Peng Fan
2015-05-26 12:16 ` Stefano Babic
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