From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Wed, 20 May 2015 13:06:21 +0200 Subject: [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT In-Reply-To: <1432088928-7414-1-git-send-email-Peng.Fan@freescale.com> References: <1432088928-7414-1-git-send-email-Peng.Fan@freescale.com> Message-ID: <201505201306.21556.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wednesday, May 20, 2015 at 04:28:48 AM, Peng Fan wrote: > We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee > that socs' cache line size is 32 bytes. > If on chips whose cache line size is 64 bytes, error occurs: Which chips are those? > NAND: ERROR: v7_dcache_inval_range - start address is not aligned - > 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - > 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - > 0xbdf1d1a0 " > Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to > CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined. > > Signed-off-by: Peng Fan Acked-by: Marek Vasut Best regards, Marek Vasut