* [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT
@ 2015-05-20 2:28 Peng Fan
2015-05-20 11:06 ` Marek Vasut
2015-05-26 12:16 ` Stefano Babic
0 siblings, 2 replies; 6+ messages in thread
From: Peng Fan @ 2015-05-20 2:28 UTC (permalink / raw)
To: u-boot
We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"
NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
arch/arm/include/asm/imx-common/dma.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h
index d5c1f7f..7d421b3 100644
--- a/arch/arm/include/asm/imx-common/dma.h
+++ b/arch/arm/include/asm/imx-common/dma.h
@@ -22,7 +22,7 @@
#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
#endif
-#define MXS_DMA_ALIGNMENT 32
+#define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN
/*
* MXS DMA channels
--
1.8.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT
2015-05-20 2:28 [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT Peng Fan
@ 2015-05-20 11:06 ` Marek Vasut
2015-05-21 1:16 ` Peng Fan
2015-05-26 12:16 ` Stefano Babic
1 sibling, 1 reply; 6+ messages in thread
From: Marek Vasut @ 2015-05-20 11:06 UTC (permalink / raw)
To: u-boot
On Wednesday, May 20, 2015 at 04:28:48 AM, Peng Fan wrote:
> We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
> that socs' cache line size is 32 bytes.
> If on chips whose cache line size is 64 bytes, error occurs:
Which chips are those?
> NAND: ERROR: v7_dcache_inval_range - start address is not aligned -
> 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned -
> 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned -
> 0xbdf1d1a0 "
> Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
> CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT
2015-05-20 11:06 ` Marek Vasut
@ 2015-05-21 1:16 ` Peng Fan
2015-05-21 1:26 ` Marek Vasut
2015-05-25 13:08 ` Peng Fan
0 siblings, 2 replies; 6+ messages in thread
From: Peng Fan @ 2015-05-21 1:16 UTC (permalink / raw)
To: u-boot
Hi Marek,
On Wed, May 20, 2015 at 01:06:21PM +0200, Marek Vasut wrote:
>On Wednesday, May 20, 2015 at 04:28:48 AM, Peng Fan wrote:
>> We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
>> that socs' cache line size is 32 bytes.
>> If on chips whose cache line size is 64 bytes, error occurs:
>
>Which chips are those?
i.MX7's L1 Cache line size is 64 bytes.
>
>> NAND: ERROR: v7_dcache_inval_range - start address is not aligned -
>> 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned -
>> 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned -
>> 0xbdf1d1a0 "
>> Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
>> CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
>>
>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>
>Acked-by: Marek Vasut <marex@denx.de>
>
>Best regards,
>Marek Vasut
Regards,
Peng.
--
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT
2015-05-21 1:16 ` Peng Fan
@ 2015-05-21 1:26 ` Marek Vasut
2015-05-25 13:08 ` Peng Fan
1 sibling, 0 replies; 6+ messages in thread
From: Marek Vasut @ 2015-05-21 1:26 UTC (permalink / raw)
To: u-boot
On Thursday, May 21, 2015 at 03:16:32 AM, Peng Fan wrote:
> Hi Marek,
Hi!
> On Wed, May 20, 2015 at 01:06:21PM +0200, Marek Vasut wrote:
> >On Wednesday, May 20, 2015 at 04:28:48 AM, Peng Fan wrote:
> >> We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not
> >> guarantee that socs' cache line size is 32 bytes.
> >
> >> If on chips whose cache line size is 64 bytes, error occurs:
> >Which chips are those?
>
> i.MX7's L1 Cache line size is 64 bytes.
Oh, I didn't know this was a public info. Oki, thanks for clarifying :)
> >> NAND: ERROR: v7_dcache_inval_range - start address is not aligned -
> >> 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned -
> >> 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned -
> >> 0xbdf1d1a0 "
> >> Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
> >> CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
> >>
> >> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> >
> >Acked-by: Marek Vasut <marex@denx.de>
> >
> >Best regards,
> >Marek Vasut
>
> Regards,
> Peng.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT
2015-05-21 1:16 ` Peng Fan
2015-05-21 1:26 ` Marek Vasut
@ 2015-05-25 13:08 ` Peng Fan
1 sibling, 0 replies; 6+ messages in thread
From: Peng Fan @ 2015-05-25 13:08 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Thu, May 21, 2015 at 09:16:32AM +0800, Peng Fan wrote:
>Hi Marek,
>
>On Wed, May 20, 2015 at 01:06:21PM +0200, Marek Vasut wrote:
>>On Wednesday, May 20, 2015 at 04:28:48 AM, Peng Fan wrote:
>>> We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
>>> that socs' cache line size is 32 bytes.
>>> If on chips whose cache line size is 64 bytes, error occurs:
>>
>>Which chips are those?
>i.MX7's L1 Cache line size is 64 bytes.
>>
>>> NAND: ERROR: v7_dcache_inval_range - start address is not aligned -
>>> 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned -
>>> 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned -
>>> 0xbdf1d1a0 "
>>> Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
>>> CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
>>>
>>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>>
>>Acked-by: Marek Vasut <marex@denx.de>
Will you apply this patch?
>>
>>Best regards,
>>Marek Vasut
>
>Regards,
>Peng.
>--
Regards,
Peng
--
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT
2015-05-20 2:28 [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT Peng Fan
2015-05-20 11:06 ` Marek Vasut
@ 2015-05-26 12:16 ` Stefano Babic
1 sibling, 0 replies; 6+ messages in thread
From: Stefano Babic @ 2015-05-26 12:16 UTC (permalink / raw)
To: u-boot
On 20/05/2015 04:28, Peng Fan wrote:
> We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
> that socs' cache line size is 32 bytes.
> If on chips whose cache line size is 64 bytes, error occurs:
> "
> NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
> ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
> ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
> "
> Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
> CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
> arch/arm/include/asm/imx-common/dma.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h
> index d5c1f7f..7d421b3 100644
> --- a/arch/arm/include/asm/imx-common/dma.h
> +++ b/arch/arm/include/asm/imx-common/dma.h
> @@ -22,7 +22,7 @@
> #define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
> #endif
>
> -#define MXS_DMA_ALIGNMENT 32
> +#define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN
>
> /*
> * MXS DMA channels
>
Applied to u-boot-imx, thanks!
Best regards,
Stefano Babic
--
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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
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2015-05-20 2:28 [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT Peng Fan
2015-05-20 11:06 ` Marek Vasut
2015-05-21 1:16 ` Peng Fan
2015-05-21 1:26 ` Marek Vasut
2015-05-25 13:08 ` Peng Fan
2015-05-26 12:16 ` Stefano Babic
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