[U-Boot] [PATCH 0/8] ARM: sunxi: Support PSCI for sun6i and sun8i

[U-Boot] [PATCH 0/8] ARM: sunxi: Support PSCI for sun6i and sun8i

[Chen-Yu Tsai]

Hi everyone,

I finally got around to rebasing and fixing up my PSCI stuff.
This series adds PSCI support for sun6i and sun8i. This is
based on sun7i PSCI support by Marc, and the SMP support
routines found in both mainline Linux and Allwinner's Android
kernel.

I've tested this on my Hummingbird A31 board and Ippo q8h v5
tablet. Given the A23 SMP routines work on the A33 as well,
I see no reason it would not work, so A33 support is included
as well, but more testing is always welcome.

Patch 1 and 2 address a build failur on sunxi/next I ran into,
which is related to the new NAND SPL support.

Patch 3 adds some comments to the sunxi PSCI code, for easier
reading.

Patch 4 moves sun7i PSCI code aside.

Patch 5 adds sun6i PSCI code. Differences from sun7i are the
separate PRCM block for power gating/clamps, and support for
more than 1 secondary CPU core.

Patch 6 enables PSCI for sun6i.

Patch 7 lets sun8i share PSCI code with sun6i. The routines
are the same, except sun8i does not have power clamps.

Patch 8 enables PSCI for sun8i (A23/A33).


Wonder if we still need the SMP support in the kernel?


Regards
ChenYu


Chen-Yu Tsai (8):
  sunxi: Only compile board_nand_init() if CONFIG_NAND is set
  sunxi: Add extra NAND pins for sun6i
  ARM: sunxi: Document registers in PSCI code
  ARM: sunxi: Make PSCI code sun7i specific
  ARM: sunxi: Add sun6i specific PSCI implementation
  ARM: sunxi: Enable PSCI for sun6i
  ARM: sunxi: Share sun6i PSCI backend with sun8i
  ARM: sunxi: Enable PSCI for sun8i

 arch/arm/cpu/armv7/sunxi/Makefile                 |  4 +-
 arch/arm/cpu/armv7/sunxi/{psci.S => psci_sun6i.S} | 81 +++++++++++++++--------
 arch/arm/cpu/armv7/sunxi/{psci.S => psci_sun7i.S} | 14 ++--
 board/sunxi/Kconfig                               |  9 +++
 board/sunxi/board.c                               |  2 +
 include/configs/sun6i.h                           |  7 ++
 include/configs/sun8i.h                           |  6 ++
 7 files changed, 87 insertions(+), 36 deletions(-)
 copy arch/arm/cpu/armv7/sunxi/{psci.S => psci_sun6i.S} (74%)
 rename arch/arm/cpu/armv7/sunxi/{psci.S => psci_sun7i.S} (94%)

-- 
2.1.4

[U-Boot] [PATCH 1/8] sunxi: Only compile board_nand_init() if CONFIG_NAND is set

[Chen-Yu Tsai]

There's no need to init NAND if we're not building with NAND support.
Wrap board_nand_init() in #ifdefs like we do for board_mmc_init().
This fixes build breaks for sun6i and sun9i. Both platforms do not
have CONFIG_NAND_SUNXI_GPC_PORTS defined.

Fixes: fbf13d684dcb ("sunxi/nand: Add support to the SPL for loading u-boot
		      from internal NAND memory")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 board/sunxi/board.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 3f23f26..f27967b 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -318,6 +318,7 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_NAND
 void board_nand_init(void)
 {
 	unsigned int pin;
@@ -330,6 +331,7 @@ void board_nand_init(void)
 	for (pin = 0; pin < ARRAY_SIZE(ports); pin++)
 		sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND);
 }
+#endif
 
 void i2c_init_board(void)
 {
-- 
2.1.4

[U-Boot] [PATCH 2/8] sunxi: Add extra NAND pins for sun6i

[Chen-Yu Tsai]

In addition to pins PC00 ~ PC15, PC24, PC25, and PC26 are mapped
to NAND0 DQS, CE2, and CE3 respectively.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 include/configs/sun6i.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
index 2c24bd2..e1263f6 100644
--- a/include/configs/sun6i.h
+++ b/include/configs/sun6i.h
@@ -22,6 +22,8 @@
 
 #define CONFIG_SUNXI_USB_PHYS	3
 
+#define CONFIG_NAND_SUNXI_GPC_PORTS	{24, 25, 26}
+
 /*
  * Include common sunxi configuration where most the settings are
  */
-- 
2.1.4

[U-Boot] [PATCH 3/8] ARM: sunxi: Document registers in PSCI code

[Chen-Yu Tsai]

The PSCI CPU_ON code accesses quite a few registers. Document
their names to make it easier to cross reference.

Also explain "lock cpu" and "unlock cpu" as enabling/disabling
debug access.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/psci.S | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 7ec0500..bbfeec8 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -165,12 +165,12 @@ psci_cpu_on:
 	str	r6, [r5]	@ Reset CPU
 
 	@ l1 invalidate
-	ldr	r6, [r0, #0x184]
+	ldr	r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
 	bic	r6, r6, r4
 	str	r6, [r0, #0x184]
 
-	@ Lock CPU
-	ldr	r6, [r0, #0x1e4]
+	@ Lock CPU (Disable external debug access)
+	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
 	bic	r6, r6, r4
 	str	r6, [r0, #0x1e4]
 
@@ -178,13 +178,13 @@ psci_cpu_on:
 	movw	r6, #0x1ff
 	movt	r6, #0
 1:	lsrs	r6, r6, #1
-	str	r6, [r0, #0x1b0]
+	str	r6, [r0, #0x1b0] @ CPU1_PWR_CLAMP
 	bne	1b
 
 	timer_wait r1, TEN_MS
 
 	@ Clear power gating
-	ldr	r6, [r0, #0x1b4]
+	ldr	r6, [r0, #0x1b4] @ CPU1_PWROFF_REG
 	bic	r6, r6, #1
 	str	r6, [r0, #0x1b4]
 
@@ -192,8 +192,8 @@ psci_cpu_on:
 	mov	r6, #3
 	str	r6, [r5]
 
-	@ Unlock CPU
-	ldr	r6, [r0, #0x1e4]
+	@ Unlock CPU (Enable external debug access)
+	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
 	orr	r6, r6, r4
 	str	r6, [r0, #0x1e4]
 
-- 
2.1.4

[U-Boot] [PATCH 3/8] ARM: sunxi: Document registers in PSCI code

[Maxime Ripard]

On Thu, May 28, 2015 at 09:25:29PM +0800, Chen-Yu Tsai wrote:
> The PSCI CPU_ON code accesses quite a few registers. Document
> their names to make it easier to cross reference.
> 
> Also explain "lock cpu" and "unlock cpu" as enabling/disabling
> debug access.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/cpu/armv7/sunxi/psci.S | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
> index 7ec0500..bbfeec8 100644
> --- a/arch/arm/cpu/armv7/sunxi/psci.S
> +++ b/arch/arm/cpu/armv7/sunxi/psci.S
> @@ -165,12 +165,12 @@ psci_cpu_on:
>  	str	r6, [r5]	@ Reset CPU
>  
>  	@ l1 invalidate
> -	ldr	r6, [r0, #0x184]
> +	ldr	r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG

Can't we use some defines instead? You seem to do that on a few
registers (mostly the GIC's), why not for these?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[U-Boot] [PATCH 3/8] ARM: sunxi: Document registers in PSCI code

[Chen-Yu Tsai]

On Thu, May 28, 2015 at 11:23 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, May 28, 2015 at 09:25:29PM +0800, Chen-Yu Tsai wrote:
>> The PSCI CPU_ON code accesses quite a few registers. Document
>> their names to make it easier to cross reference.
>>
>> Also explain "lock cpu" and "unlock cpu" as enabling/disabling
>> debug access.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  arch/arm/cpu/armv7/sunxi/psci.S | 14 +++++++-------
>>  1 file changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
>> index 7ec0500..bbfeec8 100644
>> --- a/arch/arm/cpu/armv7/sunxi/psci.S
>> +++ b/arch/arm/cpu/armv7/sunxi/psci.S
>> @@ -165,12 +165,12 @@ psci_cpu_on:
>>       str     r6, [r5]        @ Reset CPU
>>
>>       @ l1 invalidate
>> -     ldr     r6, [r0, #0x184]
>> +     ldr     r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
>
> Can't we use some defines instead? You seem to do that on a few
> registers (mostly the GIC's), why not for these?

Sure. Though to be clear GIC wasn't my work. :p

For sun6i there's a bit of offset calculating, so
we can't use defines for them all.

ChenYu

[U-Boot] [PATCH 4/8] ARM: sunxi: Make PSCI code sun7i specific

[Chen-Yu Tsai]

The PSCI code only works for sun7i. Rename it with _sun7i suffix,
and build only if building for sun7i.

This paves the way for adding PSCI support for other platforms.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/Makefile                 | 2 +-
 arch/arm/cpu/armv7/sunxi/{psci.S => psci_sun7i.S} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename arch/arm/cpu/armv7/sunxi/{psci.S => psci_sun7i.S} (100%)

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 7ef6b4c..85fbc85 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -35,7 +35,7 @@ obj-$(CONFIG_AXP221_POWER)	+= pmic_bus.o
 
 ifndef CONFIG_SPL_BUILD
 ifdef CONFIG_ARMV7_PSCI
-obj-y	+= psci.o
+obj-$(CONFIG_MACH_SUN7I)	+= psci_sun7i.o
 endif
 endif
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
similarity index 100%
rename from arch/arm/cpu/armv7/sunxi/psci.S
rename to arch/arm/cpu/armv7/sunxi/psci_sun7i.S
-- 
2.1.4

[U-Boot] [PATCH 5/8] ARM: sunxi: Add sun6i specific PSCI implementation

[Chen-Yu Tsai]

This adds PSCI support for sun6i. So far it only supports
the PWR_ON method.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/Makefile     |   1 +
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 276 ++++++++++++++++++++++++++++++++++
 2 files changed, 277 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 85fbc85..4b783e0 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_AXP221_POWER)	+= pmic_bus.o
 
 ifndef CONFIG_SPL_BUILD
 ifdef CONFIG_ARMV7_PSCI
+obj-$(CONFIG_MACH_SUN6I)	+= psci_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= psci_sun7i.o
 endif
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
new file mode 100644
index 0000000..2516804
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -0,0 +1,276 @@
+/*
+ * Copyright (C) 2015 - Chen-Yu Tsai
+ * Author: Chen-Yu Tsai <wens@csie.org>
+ *
+ * Based on psci_sun7i.S by Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <asm/gic.h>
+#include <asm/macro.h>
+#include <asm/psci.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Memory layout:
+ *
+ * SECURE_RAM to text_end :
+ *	._secure_text section
+ * text_end to ALIGN_PAGE(text_end):
+ *	nothing
+ * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
+ *	1kB of stack per CPU (4 CPUs max).
+ */
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+#define	ONE_MS			(CONFIG_TIMER_CLK_FREQ / 1000)
+#define	TEN_MS			(10 * ONE_MS)
+#define	GICD_BASE		0x1c81000
+#define	GICC_BASE		0x1c82000
+
+.macro	timer_wait	reg, ticks
+	@ Program CNTP_TVAL
+	movw	\reg, #(\ticks & 0xffff)
+	movt	\reg, #(\ticks >> 16)
+	mcr	p15, 0, \reg, c14, c2, 0
+	isb
+	@ Enable physical timer, mask interrupt
+	mov	\reg, #3
+	mcr	p15, 0, \reg, c14, c2, 1
+	@ Poll physical timer until ISTATUS is on
+1:	isb
+	mrc	p15, 0, \reg, c14, c2, 1
+	ands	\reg, \reg, #4
+	bne	1b
+	@ Disable timer
+	mov	\reg, #0
+	mcr	p15, 0, \reg, c14, c2, 1
+	isb
+.endm
+
+.globl	psci_fiq_enter
+psci_fiq_enter:
+	push	{r0-r12}
+
+	@ Switch to secure
+	mrc	p15, 0, r7, c1, c1, 0
+	bic	r8, r7, #1
+	mcr	p15, 0, r8, c1, c1, 0
+	isb
+
+	@ Validate reason based on IAR and acknowledge
+	movw	r8, #(GICC_BASE & 0xffff)
+	movt	r8, #(GICC_BASE >> 16)
+	ldr	r9, [r8, #GICC_IAR]
+	movw	r10, #0x3ff
+	movt	r10, #0
+	cmp	r9, r10			@ skip spurious interrupt 1023
+	beq	out
+	movw	r10, #0x3fe		@ ...and 1022
+	cmp	r9, r10
+	beq	out
+	str	r9, [r8, #GICC_EOIR]	@ acknowledge the interrupt
+	dsb
+
+	@ Compute CPU number
+	lsr	r9, r9, #10
+	and	r9, r9, #0xf
+
+	movw	r8, #(SUN6I_CPUCFG_BASE & 0xffff)
+	movt	r8, #(SUN6I_CPUCFG_BASE >> 16)
+
+	@ Wait for the core to enter WFI
+	lsl	r11, r9, #6		@ x64
+	add	r11, r11, r8
+
+1:	ldr	r10, [r11, #0x48]
+	tst	r10, #(1 << 2)
+	bne	2f
+	timer_wait r10, ONE_MS
+	b	1b
+
+	@ Reset CPU
+2:	mov	r10, #0
+	str	r10, [r11, #0x40]
+
+	@ Lock CPU
+	mov	r10, #1
+	lsl	r11, r10, r9		@ r11 is now CPU mask
+	ldr	r10, [r8, #0x1e4]
+	bic	r10, r10, r11
+	str	r10, [r8, #0x1e4]
+
+	movw	r8, #(SUNXI_PRCM_BASE & 0xffff)
+	movt	r8, #(SUNXI_PRCM_BASE >> 16)
+
+	@ Set power gating
+	ldr	r10, [r8, #0x100]
+	orr	r10, r10, r11
+	str	r10, [r8, #0x100]
+	timer_wait r10, ONE_MS
+
+	@ Activate power clamp
+	lsl	r12, r9, #2		@ x4
+	add	r12, r12, r8
+	mov	r10, #0xff
+	str	r10, [r12, #0x140]
+
+	movw	r8, #(SUN6I_CPUCFG_BASE & 0xffff)
+	movt	r8, #(SUN6I_CPUCFG_BASE >> 16)
+
+	@ Unlock CPU
+	ldr	r10, [r8, #0x1e4]
+	orr	r10, r10, r11
+	str	r10, [r8, #0x1e4]
+
+	@ Restore security level
+out:	mcr	p15, 0, r7, c1, c1, 0
+
+	pop	{r0-r12}
+	subs    pc, lr, #4
+
+	@ r1 = target CPU
+	@ r2 = target PC
+.globl	psci_cpu_on
+psci_cpu_on:
+	push	{lr}
+
+	mov	r0, r1
+	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
+	str	r2, [r0]		@ store target PC at stack top
+	dsb
+
+	movw	r0, #(SUN6I_CPUCFG_BASE & 0xffff)
+	movt	r0, #(SUN6I_CPUCFG_BASE >> 16)
+
+	@ CPU mask
+	and	r1, r1, #3	@ only care about first cluster
+	mov	r4, #1
+	lsl	r4, r4, r1
+
+	ldr	r6, =psci_cpu_entry
+	str	r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
+
+	@ Assert reset on target CPU
+	mov	r6, #0
+	lsl	r5, r1, #6	@ 64 bytes per CPU
+	add	r5, r5, #0x40	@ Offset from base
+	add	r5, r5, r0	@ CPU control block
+	str	r6, [r5]	@ Reset CPU
+
+	@ l1 invalidate
+	ldr	r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
+	bic	r6, r6, r4
+	str	r6, [r0, #0x184]
+
+	@ Lock CPU (Disable external debug access)
+	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
+	bic	r6, r6, r4
+	str	r6, [r0, #0x1e4]
+
+	movw	r0, #(SUNXI_PRCM_BASE & 0xffff)
+	movt	r0, #(SUNXI_PRCM_BASE >> 16)
+
+	@ Release power clamp
+	lsl	r5, r1, #2	@ 1 register per CPU
+	add	r5, r5, r0	@ PRCM
+	movw	r6, #0x1ff
+	movt	r6, #0
+1:	lsrs	r6, r6, #1
+	str	r6, [r5, #0x140] @ CPUx_PWR_CLAMP
+	bne	1b
+
+	timer_wait r6, TEN_MS
+
+	@ Clear power gating
+	ldr	r6, [r0, #0x100] @ CPU_PWROFF_GATING
+	bic	r6, r6, r4
+	str	r6, [r0, #0x100]
+
+	@ re-calculate CPU control register address
+	movw	r0, #(SUN6I_CPUCFG_BASE & 0xffff)
+	movt	r0, #(SUN6I_CPUCFG_BASE >> 16)
+
+	@ Deassert reset on target CPU
+	mov	r6, #3
+	lsl	r5, r1, #6	@ 64 bytes per CPU
+	add	r5, r5, #0x40	@ Offset from base
+	add	r5, r5, r0	@ CPU control block
+	str	r6, [r5]
+
+	@ Unlock CPU (Enable external debug access)
+	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
+	orr	r6, r6, r4
+	str	r6, [r0, #0x1e4]
+
+	mov	r0, #ARM_PSCI_RET_SUCCESS	@ Return PSCI_RET_SUCCESS
+	pop	{pc}
+
+.globl	psci_cpu_off
+psci_cpu_off:
+	bl	psci_cpu_off_common
+
+	@ Ask CPU0 to pull the rug...
+	movw	r0, #(GICD_BASE & 0xffff)
+	movt	r0, #(GICD_BASE >> 16)
+	movw	r1, #15				@ SGI15
+	movt	r1, #1				@ Target is CPU0
+	str	r1, [r0, #GICD_SGIR]
+	dsb
+
+1:	wfi
+	b	1b
+
+.globl	psci_arch_init
+psci_arch_init:
+	mov	r6, lr
+
+	movw	r4, #(GICD_BASE & 0xffff)
+	movt	r4, #(GICD_BASE >> 16)
+
+	ldr	r5, [r4, #GICD_IGROUPRn]
+	bic	r5, r5, #(1 << 15) 	@ SGI15 as Group-0
+	str	r5, [r4, #GICD_IGROUPRn]
+
+	mov	r5, #0			@ Set SGI15 priority to 0
+	strb	r5, [r4, #(GICD_IPRIORITYRn + 15)]
+
+	add	r4, r4, #0x1000		@ GICC address
+
+	mov	r5, #0xff
+	str	r5, [r4, #GICC_PMR]	@ Be cool with non-secure
+
+	ldr	r5, [r4, #GICC_CTLR]
+	orr	r5, r5, #(1 << 3)	@ Switch FIQEn on
+	str	r5, [r4, #GICC_CTLR]
+
+	mrc	p15, 0, r5, c1, c1, 0	@ Read SCR
+	orr	r5, r5, #4		@ Enable FIQ in monitor mode
+	bic	r5, r5, #1		@ Secure mode
+	mcr	p15, 0, r5, c1, c1, 0	@ Write SCR
+	isb
+
+	bl	psci_get_cpu_id		@ CPU ID => r0
+	bl	psci_get_cpu_stack_top	@ stack top => r0
+	mov	sp, r0
+
+	bx	r6
+
+	.globl psci_text_end
+psci_text_end:
+	.popsection
-- 
2.1.4

[U-Boot] [PATCH 5/8] ARM: sunxi: Add sun6i specific PSCI implementation

[Maxime Ripard]

On Thu, May 28, 2015 at 09:25:31PM +0800, Chen-Yu Tsai wrote:
> This adds PSCI support for sun6i. So far it only supports
> the PWR_ON method.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/cpu/armv7/sunxi/Makefile     |   1 +
>  arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 276 ++++++++++++++++++++++++++++++++++
>  2 files changed, 277 insertions(+)
>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
> 
> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
> index 85fbc85..4b783e0 100644
> --- a/arch/arm/cpu/armv7/sunxi/Makefile
> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
> @@ -35,6 +35,7 @@ obj-$(CONFIG_AXP221_POWER)	+= pmic_bus.o
>  
>  ifndef CONFIG_SPL_BUILD
>  ifdef CONFIG_ARMV7_PSCI
> +obj-$(CONFIG_MACH_SUN6I)	+= psci_sun6i.o
>  obj-$(CONFIG_MACH_SUN7I)	+= psci_sun7i.o
>  endif
>  endif
> diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
> new file mode 100644
> index 0000000..2516804
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
> @@ -0,0 +1,276 @@
> +/*
> + * Copyright (C) 2015 - Chen-Yu Tsai
> + * Author: Chen-Yu Tsai <wens@csie.org>
> + *
> + * Based on psci_sun7i.S by Marc Zyngier <marc.zyngier@arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <config.h>
> +#include <asm/gic.h>
> +#include <asm/macro.h>
> +#include <asm/psci.h>
> +#include <asm/arch/cpu.h>
> +
> +/*
> + * Memory layout:
> + *
> + * SECURE_RAM to text_end :
> + *	._secure_text section
> + * text_end to ALIGN_PAGE(text_end):
> + *	nothing
> + * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
> + *	1kB of stack per CPU (4 CPUs max).
> + */
> +
> +	.pushsection ._secure.text, "ax"
> +
> +	.arch_extension sec
> +
> +#define	ONE_MS			(CONFIG_TIMER_CLK_FREQ / 1000)
> +#define	TEN_MS			(10 * ONE_MS)
> +#define	GICD_BASE		0x1c81000
> +#define	GICC_BASE		0x1c82000
> +
> +.macro	timer_wait	reg, ticks
> +	@ Program CNTP_TVAL
> +	movw	\reg, #(\ticks & 0xffff)
> +	movt	\reg, #(\ticks >> 16)
> +	mcr	p15, 0, \reg, c14, c2, 0
> +	isb
> +	@ Enable physical timer, mask interrupt
> +	mov	\reg, #3
> +	mcr	p15, 0, \reg, c14, c2, 1
> +	@ Poll physical timer until ISTATUS is on
> +1:	isb
> +	mrc	p15, 0, \reg, c14, c2, 1
> +	ands	\reg, \reg, #4
> +	bne	1b
> +	@ Disable timer
> +	mov	\reg, #0
> +	mcr	p15, 0, \reg, c14, c2, 1
> +	isb
> +.endm
> +

I think I saw some patch to factorize that out. In the Tegra K1 PSCI
patches iirc.

> +.globl	psci_fiq_enter
> +psci_fiq_enter:
> +	push	{r0-r12}
> +
> +	@ Switch to secure
> +	mrc	p15, 0, r7, c1, c1, 0
> +	bic	r8, r7, #1
> +	mcr	p15, 0, r8, c1, c1, 0
> +	isb
> +
> +	@ Validate reason based on IAR and acknowledge
> +	movw	r8, #(GICC_BASE & 0xffff)
> +	movt	r8, #(GICC_BASE >> 16)
> +	ldr	r9, [r8, #GICC_IAR]
> +	movw	r10, #0x3ff
> +	movt	r10, #0
> +	cmp	r9, r10			@ skip spurious interrupt 1023
> +	beq	out
> +	movw	r10, #0x3fe		@ ...and 1022

Maybe we could add some defines for these spurious interrupts values ?

> +.globl	psci_arch_init
> +psci_arch_init:
> +	mov	r6, lr
> +
> +	movw	r4, #(GICD_BASE & 0xffff)
> +	movt	r4, #(GICD_BASE >> 16)
> +
> +	ldr	r5, [r4, #GICD_IGROUPRn]
> +	bic	r5, r5, #(1 << 15) 	@ SGI15 as Group-0
> +	str	r5, [r4, #GICD_IGROUPRn]
> +
> +	mov	r5, #0			@ Set SGI15 priority to 0
> +	strb	r5, [r4, #(GICD_IPRIORITYRn + 15)]
> +
> +	add	r4, r4, #0x1000		@ GICC address
> +
> +	mov	r5, #0xff
> +	str	r5, [r4, #GICC_PMR]	@ Be cool with non-secure
> +
> +	ldr	r5, [r4, #GICC_CTLR]
> +	orr	r5, r5, #(1 << 3)	@ Switch FIQEn on
> +	str	r5, [r4, #GICC_CTLR]
> +
> +	mrc	p15, 0, r5, c1, c1, 0	@ Read SCR
> +	orr	r5, r5, #4		@ Enable FIQ in monitor mode
> +	bic	r5, r5, #1		@ Secure mode
> +	mcr	p15, 0, r5, c1, c1, 0	@ Write SCR
> +	isb
> +
> +	bl	psci_get_cpu_id		@ CPU ID => r0
> +	bl	psci_get_cpu_stack_top	@ stack top => r0
> +	mov	sp, r0
> +
> +	bx	r6
> +
> +	.globl psci_text_end

Isn't it exactly the same function than the A20's? Maybe that can be
shared?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[U-Boot] [PATCH 5/8] ARM: sunxi: Add sun6i specific PSCI implementation

[Chen-Yu Tsai]

On Thu, May 28, 2015 at 11:22 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, May 28, 2015 at 09:25:31PM +0800, Chen-Yu Tsai wrote:
>> This adds PSCI support for sun6i. So far it only supports
>> the PWR_ON method.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  arch/arm/cpu/armv7/sunxi/Makefile     |   1 +
>>  arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 276 ++++++++++++++++++++++++++++++++++
>>  2 files changed, 277 insertions(+)
>>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>>
>> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
>> index 85fbc85..4b783e0 100644
>> --- a/arch/arm/cpu/armv7/sunxi/Makefile
>> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
>> @@ -35,6 +35,7 @@ obj-$(CONFIG_AXP221_POWER)  += pmic_bus.o
>>
>>  ifndef CONFIG_SPL_BUILD
>>  ifdef CONFIG_ARMV7_PSCI
>> +obj-$(CONFIG_MACH_SUN6I)     += psci_sun6i.o
>>  obj-$(CONFIG_MACH_SUN7I)     += psci_sun7i.o
>>  endif
>>  endif
>> diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>> new file mode 100644
>> index 0000000..2516804
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>> @@ -0,0 +1,276 @@
>> +/*
>> + * Copyright (C) 2015 - Chen-Yu Tsai
>> + * Author: Chen-Yu Tsai <wens@csie.org>
>> + *
>> + * Based on psci_sun7i.S by Marc Zyngier <marc.zyngier@arm.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include <config.h>
>> +#include <asm/gic.h>
>> +#include <asm/macro.h>
>> +#include <asm/psci.h>
>> +#include <asm/arch/cpu.h>
>> +
>> +/*
>> + * Memory layout:
>> + *
>> + * SECURE_RAM to text_end :
>> + *   ._secure_text section
>> + * text_end to ALIGN_PAGE(text_end):
>> + *   nothing
>> + * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
>> + *   1kB of stack per CPU (4 CPUs max).
>> + */
>> +
>> +     .pushsection ._secure.text, "ax"
>> +
>> +     .arch_extension sec
>> +
>> +#define      ONE_MS                  (CONFIG_TIMER_CLK_FREQ / 1000)
>> +#define      TEN_MS                  (10 * ONE_MS)
>> +#define      GICD_BASE               0x1c81000
>> +#define      GICC_BASE               0x1c82000
>> +
>> +.macro       timer_wait      reg, ticks
>> +     @ Program CNTP_TVAL
>> +     movw    \reg, #(\ticks & 0xffff)
>> +     movt    \reg, #(\ticks >> 16)
>> +     mcr     p15, 0, \reg, c14, c2, 0
>> +     isb
>> +     @ Enable physical timer, mask interrupt
>> +     mov     \reg, #3
>> +     mcr     p15, 0, \reg, c14, c2, 1
>> +     @ Poll physical timer until ISTATUS is on
>> +1:   isb
>> +     mrc     p15, 0, \reg, c14, c2, 1
>> +     ands    \reg, \reg, #4
>> +     bne     1b
>> +     @ Disable timer
>> +     mov     \reg, #0
>> +     mcr     p15, 0, \reg, c14, c2, 1
>> +     isb
>> +.endm
>> +
>
> I think I saw some patch to factorize that out. In the Tegra K1 PSCI
> patches iirc.

Waiting for v2: https://patchwork.ozlabs.org/patch/471694/

>> +.globl       psci_fiq_enter
>> +psci_fiq_enter:
>> +     push    {r0-r12}
>> +
>> +     @ Switch to secure
>> +     mrc     p15, 0, r7, c1, c1, 0
>> +     bic     r8, r7, #1
>> +     mcr     p15, 0, r8, c1, c1, 0
>> +     isb
>> +
>> +     @ Validate reason based on IAR and acknowledge
>> +     movw    r8, #(GICC_BASE & 0xffff)
>> +     movt    r8, #(GICC_BASE >> 16)
>> +     ldr     r9, [r8, #GICC_IAR]
>> +     movw    r10, #0x3ff
>> +     movt    r10, #0
>> +     cmp     r9, r10                 @ skip spurious interrupt 1023
>> +     beq     out
>> +     movw    r10, #0x3fe             @ ...and 1022
>
> Maybe we could add some defines for these spurious interrupts values ?

From the GIC spec:

The read returns a spurious interrupt ID of 1023 if any of the
following apply:
  - forwarding of interrupts by the Distributor to the CPU interface
    is disabled
  - signaling of interrupts by the CPU interface to the connected
    processor is disabled
  - no pending interrupt on the CPU interface has sufficient priority
    for the interface to signal it to the processor.

Likewise, 1022 means group 0 secure interrupts aren't forwarded to
the processor.

So my understanding is that 1022/1023 just means there's nothing
for the processor to process. Maybe a note referring to the spec
would be enough?

>> +.globl       psci_arch_init
>> +psci_arch_init:
>> +     mov     r6, lr
>> +
>> +     movw    r4, #(GICD_BASE & 0xffff)
>> +     movt    r4, #(GICD_BASE >> 16)
>> +
>> +     ldr     r5, [r4, #GICD_IGROUPRn]
>> +     bic     r5, r5, #(1 << 15)      @ SGI15 as Group-0
>> +     str     r5, [r4, #GICD_IGROUPRn]
>> +
>> +     mov     r5, #0                  @ Set SGI15 priority to 0
>> +     strb    r5, [r4, #(GICD_IPRIORITYRn + 15)]
>> +
>> +     add     r4, r4, #0x1000         @ GICC address
>> +
>> +     mov     r5, #0xff
>> +     str     r5, [r4, #GICC_PMR]     @ Be cool with non-secure
>> +
>> +     ldr     r5, [r4, #GICC_CTLR]
>> +     orr     r5, r5, #(1 << 3)       @ Switch FIQEn on
>> +     str     r5, [r4, #GICC_CTLR]
>> +
>> +     mrc     p15, 0, r5, c1, c1, 0   @ Read SCR
>> +     orr     r5, r5, #4              @ Enable FIQ in monitor mode
>> +     bic     r5, r5, #1              @ Secure mode
>> +     mcr     p15, 0, r5, c1, c1, 0   @ Write SCR
>> +     isb
>> +
>> +     bl      psci_get_cpu_id         @ CPU ID => r0
>> +     bl      psci_get_cpu_stack_top  @ stack top => r0
>> +     mov     sp, r0
>> +
>> +     bx      r6
>> +
>> +     .globl psci_text_end
>
> Isn't it exactly the same function than the A20's? Maybe that can be
> shared?

Good idea. This might even be shared by some other platforms.
"psci_text_end" should always be linked in last though.


ChenYu

[U-Boot] [PATCH 5/8] ARM: sunxi: Add sun6i specific PSCI implementation

[Hans de Goede]

Hi,

On 29-05-15 05:08, Chen-Yu Tsai wrote:
> On Thu, May 28, 2015 at 11:22 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
>> On Thu, May 28, 2015 at 09:25:31PM +0800, Chen-Yu Tsai wrote:
>>> This adds PSCI support for sun6i. So far it only supports
>>> the PWR_ON method.
>>>
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>> ---
>>>   arch/arm/cpu/armv7/sunxi/Makefile     |   1 +
>>>   arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 276 ++++++++++++++++++++++++++++++++++
>>>   2 files changed, 277 insertions(+)
>>>   create mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>>>
>>> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
>>> index 85fbc85..4b783e0 100644
>>> --- a/arch/arm/cpu/armv7/sunxi/Makefile
>>> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
>>> @@ -35,6 +35,7 @@ obj-$(CONFIG_AXP221_POWER)  += pmic_bus.o
>>>
>>>   ifndef CONFIG_SPL_BUILD
>>>   ifdef CONFIG_ARMV7_PSCI
>>> +obj-$(CONFIG_MACH_SUN6I)     += psci_sun6i.o
>>>   obj-$(CONFIG_MACH_SUN7I)     += psci_sun7i.o
>>>   endif
>>>   endif
>>> diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>>> new file mode 100644
>>> index 0000000..2516804
>>> --- /dev/null
>>> +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>>> @@ -0,0 +1,276 @@
>>> +/*
>>> + * Copyright (C) 2015 - Chen-Yu Tsai
>>> + * Author: Chen-Yu Tsai <wens@csie.org>
>>> + *
>>> + * Based on psci_sun7i.S by Marc Zyngier <marc.zyngier@arm.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>>> + */
>>> +
>>> +#include <config.h>
>>> +#include <asm/gic.h>
>>> +#include <asm/macro.h>
>>> +#include <asm/psci.h>
>>> +#include <asm/arch/cpu.h>
>>> +
>>> +/*
>>> + * Memory layout:
>>> + *
>>> + * SECURE_RAM to text_end :
>>> + *   ._secure_text section
>>> + * text_end to ALIGN_PAGE(text_end):
>>> + *   nothing
>>> + * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
>>> + *   1kB of stack per CPU (4 CPUs max).
>>> + */
>>> +
>>> +     .pushsection ._secure.text, "ax"
>>> +
>>> +     .arch_extension sec
>>> +
>>> +#define      ONE_MS                  (CONFIG_TIMER_CLK_FREQ / 1000)
>>> +#define      TEN_MS                  (10 * ONE_MS)
>>> +#define      GICD_BASE               0x1c81000
>>> +#define      GICC_BASE               0x1c82000
>>> +
>>> +.macro       timer_wait      reg, ticks
>>> +     @ Program CNTP_TVAL
>>> +     movw    \reg, #(\ticks & 0xffff)
>>> +     movt    \reg, #(\ticks >> 16)
>>> +     mcr     p15, 0, \reg, c14, c2, 0
>>> +     isb
>>> +     @ Enable physical timer, mask interrupt
>>> +     mov     \reg, #3
>>> +     mcr     p15, 0, \reg, c14, c2, 1
>>> +     @ Poll physical timer until ISTATUS is on
>>> +1:   isb
>>> +     mrc     p15, 0, \reg, c14, c2, 1
>>> +     ands    \reg, \reg, #4
>>> +     bne     1b
>>> +     @ Disable timer
>>> +     mov     \reg, #0
>>> +     mcr     p15, 0, \reg, c14, c2, 1
>>> +     isb
>>> +.endm
>>> +
>>
>> I think I saw some patch to factorize that out. In the Tegra K1 PSCI
>> patches iirc.
>
> Waiting for v2: https://patchwork.ozlabs.org/patch/471694/

Note I plan to merge this patch-set as is. I agree that factoring out
this bit into a helper is a good idea, but that can be done as a
later cleanup.

Regards,

Hans

[U-Boot] [PATCH 5/8] ARM: sunxi: Add sun6i specific PSCI implementation

[Maxime Ripard]

On Fri, May 29, 2015 at 11:08:43AM +0800, Chen-Yu Tsai wrote:
> >> +.globl       psci_fiq_enter
> >> +psci_fiq_enter:
> >> +     push    {r0-r12}
> >> +
> >> +     @ Switch to secure
> >> +     mrc     p15, 0, r7, c1, c1, 0
> >> +     bic     r8, r7, #1
> >> +     mcr     p15, 0, r8, c1, c1, 0
> >> +     isb
> >> +
> >> +     @ Validate reason based on IAR and acknowledge
> >> +     movw    r8, #(GICC_BASE & 0xffff)
> >> +     movt    r8, #(GICC_BASE >> 16)
> >> +     ldr     r9, [r8, #GICC_IAR]
> >> +     movw    r10, #0x3ff
> >> +     movt    r10, #0
> >> +     cmp     r9, r10                 @ skip spurious interrupt 1023
> >> +     beq     out
> >> +     movw    r10, #0x3fe             @ ...and 1022
> >
> > Maybe we could add some defines for these spurious interrupts values ?
> 
> From the GIC spec:
> 
> The read returns a spurious interrupt ID of 1023 if any of the
> following apply:
>   - forwarding of interrupts by the Distributor to the CPU interface
>     is disabled
>   - signaling of interrupts by the CPU interface to the connected
>     processor is disabled
>   - no pending interrupt on the CPU interface has sufficient priority
>     for the interface to signal it to the processor.
> 
> Likewise, 1022 means group 0 secure interrupts aren't forwarded to
> the processor.
> 
> So my understanding is that 1022/1023 just means there's nothing
> for the processor to process. Maybe a note referring to the spec
> would be enough?

Sorry, that's not what I meant.

What I meant was to do

#define GIC_SPURIOUS_INTERRUPT	1023

movw	r10, #GIC_SPURIOUS_INTERRUPT.

> 
> >> +.globl       psci_arch_init
> >> +psci_arch_init:
> >> +     mov     r6, lr
> >> +
> >> +     movw    r4, #(GICD_BASE & 0xffff)
> >> +     movt    r4, #(GICD_BASE >> 16)
> >> +
> >> +     ldr     r5, [r4, #GICD_IGROUPRn]
> >> +     bic     r5, r5, #(1 << 15)      @ SGI15 as Group-0
> >> +     str     r5, [r4, #GICD_IGROUPRn]
> >> +
> >> +     mov     r5, #0                  @ Set SGI15 priority to 0
> >> +     strb    r5, [r4, #(GICD_IPRIORITYRn + 15)]
> >> +
> >> +     add     r4, r4, #0x1000         @ GICC address
> >> +
> >> +     mov     r5, #0xff
> >> +     str     r5, [r4, #GICC_PMR]     @ Be cool with non-secure
> >> +
> >> +     ldr     r5, [r4, #GICC_CTLR]
> >> +     orr     r5, r5, #(1 << 3)       @ Switch FIQEn on
> >> +     str     r5, [r4, #GICC_CTLR]
> >> +
> >> +     mrc     p15, 0, r5, c1, c1, 0   @ Read SCR
> >> +     orr     r5, r5, #4              @ Enable FIQ in monitor mode
> >> +     bic     r5, r5, #1              @ Secure mode
> >> +     mcr     p15, 0, r5, c1, c1, 0   @ Write SCR
> >> +     isb
> >> +
> >> +     bl      psci_get_cpu_id         @ CPU ID => r0
> >> +     bl      psci_get_cpu_stack_top  @ stack top => r0
> >> +     mov     sp, r0
> >> +
> >> +     bx      r6
> >> +
> >> +     .globl psci_text_end
> >
> > Isn't it exactly the same function than the A20's? Maybe that can be
> > shared?
> 
> Good idea. This might even be shared by some other platforms.
> "psci_text_end" should always be linked in last though.

Maybe that can be generated directly by the linker script at the end
of the PSCI text section?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[U-Boot] [PATCH 6/8] ARM: sunxi: Enable PSCI for sun6i

[Chen-Yu Tsai]

Now that we have a PSCI backend for sun6i, enable it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 board/sunxi/Kconfig     | 3 +++
 include/configs/sun6i.h | 5 +++++
 2 files changed, 8 insertions(+)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index c6c876d..64d2af8 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -35,8 +35,11 @@ config MACH_SUN5I
 config MACH_SUN6I
 	bool "sun6i (Allwinner A31)"
 	select CPU_V7
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
+	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN7I
 	bool "sun7i (Allwinner A20)"
diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
index e1263f6..a0ebc7e 100644
--- a/include/configs/sun6i.h
+++ b/include/configs/sun6i.h
@@ -22,6 +22,11 @@
 
 #define CONFIG_SUNXI_USB_PHYS	3
 
+#define CONFIG_ARMV7_PSCI		1
+#define CONFIG_ARMV7_PSCI_NR_CPUS	4
+#define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
+#define CONFIG_TIMER_CLK_FREQ		24000000
+
 #define CONFIG_NAND_SUNXI_GPC_PORTS	{24, 25, 26}
 
 /*
-- 
2.1.4

[U-Boot] [PATCH 7/8] ARM: sunxi: Share sun6i PSCI backend with sun8i

[Chen-Yu Tsai]

sun8i can share the PSCI backend with sun6i. Only difference
is sun8i does not have CPU power clamp controls.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/Makefile     | 1 +
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 4b783e0..76c7e55 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -37,6 +37,7 @@ ifndef CONFIG_SPL_BUILD
 ifdef CONFIG_ARMV7_PSCI
 obj-$(CONFIG_MACH_SUN6I)	+= psci_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= psci_sun7i.o
+obj-$(CONFIG_MACH_SUN8I)	+= psci_sun6i.o
 endif
 endif
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 2516804..d4cb51e 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -124,11 +124,13 @@ psci_fiq_enter:
 	str	r10, [r8, #0x100]
 	timer_wait r10, ONE_MS
 
+#ifdef CONFIG_MACH_SUN6I
 	@ Activate power clamp
 	lsl	r12, r9, #2		@ x4
 	add	r12, r12, r8
 	mov	r10, #0xff
 	str	r10, [r12, #0x140]
+#endif
 
 	movw	r8, #(SUN6I_CPUCFG_BASE & 0xffff)
 	movt	r8, #(SUN6I_CPUCFG_BASE >> 16)
@@ -186,6 +188,7 @@ psci_cpu_on:
 	movw	r0, #(SUNXI_PRCM_BASE & 0xffff)
 	movt	r0, #(SUNXI_PRCM_BASE >> 16)
 
+#ifdef CONFIG_MACH_SUN6I
 	@ Release power clamp
 	lsl	r5, r1, #2	@ 1 register per CPU
 	add	r5, r5, r0	@ PRCM
@@ -194,6 +197,7 @@ psci_cpu_on:
 1:	lsrs	r6, r6, #1
 	str	r6, [r5, #0x140] @ CPUx_PWR_CLAMP
 	bne	1b
+#endif
 
 	timer_wait r6, TEN_MS
 
-- 
2.1.4

[U-Boot] [PATCH 8/8] ARM: sunxi: Enable PSCI for sun8i

[Chen-Yu Tsai]

sun8i uses the same PSCI backend as sun6i, without power clamps.
Since there is no secure SRAM, the backend is placed at the end
of DRAM.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 board/sunxi/Kconfig     | 6 ++++++
 include/configs/sun8i.h | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 64d2af8..8e27396 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -53,14 +53,20 @@ config MACH_SUN7I
 config MACH_SUN8I_A23
 	bool "sun8i (Allwinner A23)"
 	select CPU_V7
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
+	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN8I_A33
 	bool "sun8i (Allwinner A33)"
 	select CPU_V7
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
+	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN9I
 	bool "sun9i (Allwinner A80)"
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index cd33758..fe8c511 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -20,11 +20,17 @@
 
 #define CONFIG_SUNXI_USB_PHYS	2
 
+#define CONFIG_ARMV7_PSCI		1
 #if defined(CONFIG_MACH_SUN8I_A23)
+#define CONFIG_ARMV7_PSCI_NR_CPUS	2
 #define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18}
 #elif defined(CONFIG_MACH_SUN8I_A33)
+#define CONFIG_ARMV7_PSCI_NR_CPUS	4
 #define CONFIG_NAND_SUNXI_GPC_PORTS	{16}
+#else
+#error Unsupported sun8i variant
 #endif
+#define CONFIG_TIMER_CLK_FREQ		24000000
 
 /*
  * Include common sunxi configuration where most the settings are
-- 
2.1.4

[U-Boot] [PATCH 0/8] ARM: sunxi: Support PSCI for sun6i and sun8i

[Maxime Ripard]

Hi Chen-Yu,

On Thu, May 28, 2015 at 09:25:26PM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
> 
> I finally got around to rebasing and fixing up my PSCI stuff.
> This series adds PSCI support for sun6i and sun8i. This is
> based on sun7i PSCI support by Marc, and the SMP support
> routines found in both mainline Linux and Allwinner's Android
> kernel.

This is great, thanks!

> I've tested this on my Hummingbird A31 board and Ippo q8h v5
> tablet. Given the A23 SMP routines work on the A33 as well,
> I see no reason it would not work, so A33 support is included
> as well, but more testing is always welcome.

Yeah, and we can expect it to work on the H3 and R16 as well.

> Patch 1 and 2 address a build failur on sunxi/next I ran into,
> which is related to the new NAND SPL support.
> 
> Patch 3 adds some comments to the sunxi PSCI code, for easier
> reading.
> 
> Patch 4 moves sun7i PSCI code aside.
> 
> Patch 5 adds sun6i PSCI code. Differences from sun7i are the
> separate PRCM block for power gating/clamps, and support for
> more than 1 secondary CPU core.
> 
> Patch 6 enables PSCI for sun6i.
> 
> Patch 7 lets sun8i share PSCI code with sun6i. The routines
> are the same, except sun8i does not have power clamps.
> 
> Patch 8 enables PSCI for sun8i (A23/A33).
> 
> Wonder if we still need the SMP support in the kernel?

Eventually, we can remove it.

However, I think we should wait a bit before doing so. We have a few
things that will be required before that:
  - That these patches get merged (obviously)
  - That we have a way to replace the Allwinner bootloader in NAND on
    these SoCs. That's especially true on the A31, which will boot on
    NAND by default. We don't look so far off though.
  - That these patches get into enough u-boot releases that we can
    expect that most of the users to have been moved over (I'd say
    something like 2-3 releases)

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[U-Boot] [PATCH 0/8] ARM: sunxi: Support PSCI for sun6i and sun8i

[Chen-Yu Tsai]

Hi,

On Thu, May 28, 2015 at 11:31 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Chen-Yu,
>
> On Thu, May 28, 2015 at 09:25:26PM +0800, Chen-Yu Tsai wrote:
>> Hi everyone,
>>
>> I finally got around to rebasing and fixing up my PSCI stuff.
>> This series adds PSCI support for sun6i and sun8i. This is
>> based on sun7i PSCI support by Marc, and the SMP support
>> routines found in both mainline Linux and Allwinner's Android
>> kernel.
>
> This is great, thanks!
>
>> I've tested this on my Hummingbird A31 board and Ippo q8h v5
>> tablet. Given the A23 SMP routines work on the A33 as well,
>> I see no reason it would not work, so A33 support is included
>> as well, but more testing is always welcome.
>
> Yeah, and we can expect it to work on the H3 and R16 as well.
>
>> Patch 1 and 2 address a build failur on sunxi/next I ran into,
>> which is related to the new NAND SPL support.
>>
>> Patch 3 adds some comments to the sunxi PSCI code, for easier
>> reading.
>>
>> Patch 4 moves sun7i PSCI code aside.
>>
>> Patch 5 adds sun6i PSCI code. Differences from sun7i are the
>> separate PRCM block for power gating/clamps, and support for
>> more than 1 secondary CPU core.
>>
>> Patch 6 enables PSCI for sun6i.
>>
>> Patch 7 lets sun8i share PSCI code with sun6i. The routines
>> are the same, except sun8i does not have power clamps.
>>
>> Patch 8 enables PSCI for sun8i (A23/A33).
>>
>> Wonder if we still need the SMP support in the kernel?
>
> Eventually, we can remove it.
>
> However, I think we should wait a bit before doing so. We have a few
> things that will be required before that:
>   - That these patches get merged (obviously)

Let's see what the maintainers say. :)

>   - That we have a way to replace the Allwinner bootloader in NAND on
>     these SoCs. That's especially true on the A31, which will boot on
>     NAND by default. We don't look so far off though.

Hmm... Is this somehow related? AFAIK most people can use mmc0, and
at least my NAND boot0 seems to check mmc0 for a valid signature,
and reboot into that.

>   - That these patches get into enough u-boot releases that we can
>     expect that most of the users to have been moved over (I'd say
>     something like 2-3 releases)

Yeah, that seems like a safe bet.

Thanks!
ChenYu

[U-Boot] [PATCH 0/8] ARM: sunxi: Support PSCI for sun6i and sun8i

[Maxime Ripard]

On Fri, May 29, 2015 at 11:15:19AM +0800, Chen-Yu Tsai wrote:
> >   - That we have a way to replace the Allwinner bootloader in NAND on
> >     these SoCs. That's especially true on the A31, which will boot on
> >     NAND by default. We don't look so far off though.
> 
> Hmm... Is this somehow related? AFAIK most people can use mmc0, and
> at least my NAND boot0 seems to check mmc0 for a valid signature,
> and reboot into that.

I guess it depends on the A31 board then. I have a board here that
will completely ignore the MMC unless you press a button.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[U-Boot] [PATCH 0/8] ARM: sunxi: Support PSCI for sun6i and sun8i

[Hans de Goede]

Hi,

On 28-05-15 15:25, Chen-Yu Tsai wrote:
> Hi everyone,
>
> I finally got around to rebasing and fixing up my PSCI stuff.
> This series adds PSCI support for sun6i and sun8i. This is
> based on sun7i PSCI support by Marc, and the SMP support
> routines found in both mainline Linux and Allwinner's Android
> kernel.
>
> I've tested this on my Hummingbird A31 board and Ippo q8h v5
> tablet. Given the A23 SMP routines work on the A33 as well,
> I see no reason it would not work, so A33 support is included
> as well, but more testing is always welcome.

Thanks for your work on this! I've merged this
into u-boot-sunxi/next, and tested it on sun6i, sun7i,
sun8i-a23 and sun8i-a33 and it works fine everywhere.

> Patch 1 and 2 address a build failur on sunxi/next I ran into,
> which is related to the new NAND SPL support.

Thanks I've squashed these into the patch causing the build
failures in the first place.

> Patch 3 adds some comments to the sunxi PSCI code, for easier
> reading.
>
> Patch 4 moves sun7i PSCI code aside.
>
> Patch 5 adds sun6i PSCI code. Differences from sun7i are the
> separate PRCM block for power gating/clamps, and support for
> more than 1 secondary CPU core.
>
> Patch 6 enables PSCI for sun6i.
>
> Patch 7 lets sun8i share PSCI code with sun6i. The routines
> are the same, except sun8i does not have power clamps.
>
> Patch 8 enables PSCI for sun8i (A23/A33).

And I've done a normal merge of the rest, and after testing
pushed u-boot-sunxi/next to u-boot-sunxi/master and send
a pull-req to Tom to get this included into u-boot 2015.07

Regards,

Hans