[U-Boot] [PATCH 5/8] ARM: sunxi: Add sun6i specific PSCI implementation

[Maxime Ripard <maxime.ripard@free-electrons.com>]

On Fri, May 29, 2015 at 11:08:43AM +0800, Chen-Yu Tsai wrote:
> >> +.globl       psci_fiq_enter
> >> +psci_fiq_enter:
> >> +     push    {r0-r12}
> >> +
> >> +     @ Switch to secure
> >> +     mrc     p15, 0, r7, c1, c1, 0
> >> +     bic     r8, r7, #1
> >> +     mcr     p15, 0, r8, c1, c1, 0
> >> +     isb
> >> +
> >> +     @ Validate reason based on IAR and acknowledge
> >> +     movw    r8, #(GICC_BASE & 0xffff)
> >> +     movt    r8, #(GICC_BASE >> 16)
> >> +     ldr     r9, [r8, #GICC_IAR]
> >> +     movw    r10, #0x3ff
> >> +     movt    r10, #0
> >> +     cmp     r9, r10                 @ skip spurious interrupt 1023
> >> +     beq     out
> >> +     movw    r10, #0x3fe             @ ...and 1022
> >
> > Maybe we could add some defines for these spurious interrupts values ?
> 
> From the GIC spec:
> 
> The read returns a spurious interrupt ID of 1023 if any of the
> following apply:
>   - forwarding of interrupts by the Distributor to the CPU interface
>     is disabled
>   - signaling of interrupts by the CPU interface to the connected
>     processor is disabled
>   - no pending interrupt on the CPU interface has sufficient priority
>     for the interface to signal it to the processor.
> 
> Likewise, 1022 means group 0 secure interrupts aren't forwarded to
> the processor.
> 
> So my understanding is that 1022/1023 just means there's nothing
> for the processor to process. Maybe a note referring to the spec
> would be enough?

Sorry, that's not what I meant.

What I meant was to do

#define GIC_SPURIOUS_INTERRUPT	1023

movw	r10, #GIC_SPURIOUS_INTERRUPT.

> 
> >> +.globl       psci_arch_init
> >> +psci_arch_init:
> >> +     mov     r6, lr
> >> +
> >> +     movw    r4, #(GICD_BASE & 0xffff)
> >> +     movt    r4, #(GICD_BASE >> 16)
> >> +
> >> +     ldr     r5, [r4, #GICD_IGROUPRn]
> >> +     bic     r5, r5, #(1 << 15)      @ SGI15 as Group-0
> >> +     str     r5, [r4, #GICD_IGROUPRn]
> >> +
> >> +     mov     r5, #0                  @ Set SGI15 priority to 0
> >> +     strb    r5, [r4, #(GICD_IPRIORITYRn + 15)]
> >> +
> >> +     add     r4, r4, #0x1000         @ GICC address
> >> +
> >> +     mov     r5, #0xff
> >> +     str     r5, [r4, #GICC_PMR]     @ Be cool with non-secure
> >> +
> >> +     ldr     r5, [r4, #GICC_CTLR]
> >> +     orr     r5, r5, #(1 << 3)       @ Switch FIQEn on
> >> +     str     r5, [r4, #GICC_CTLR]
> >> +
> >> +     mrc     p15, 0, r5, c1, c1, 0   @ Read SCR
> >> +     orr     r5, r5, #4              @ Enable FIQ in monitor mode
> >> +     bic     r5, r5, #1              @ Secure mode
> >> +     mcr     p15, 0, r5, c1, c1, 0   @ Write SCR
> >> +     isb
> >> +
> >> +     bl      psci_get_cpu_id         @ CPU ID => r0
> >> +     bl      psci_get_cpu_stack_top  @ stack top => r0
> >> +     mov     sp, r0
> >> +
> >> +     bx      r6
> >> +
> >> +     .globl psci_text_end
> >
> > Isn't it exactly the same function than the A20's? Maybe that can be
> > shared?
> 
> Good idea. This might even be shared by some other platforms.
> "psci_text_end" should always be linked in last though.

Maybe that can be generated directly by the linker script at the end
of the PSCI text section?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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