[U-Boot] [PATCH 2/8] imx: mx6: Add MX6DQP CPU rev type

Stefano Babic
2015-06-10T09:19:07Z

Hi Peng,

On 10/06/2015 10:06, Peng Fan wrote:
> Add new cpu type for i.MX6DQP and providing a dynamical
> detecting function.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Signed-off-by: Ye.Li <B37916@freescale.com>
> ---
> arch/arm/cpu/armv7/mx6/soc.c | 4 +++-
> arch/arm/include/asm/arch-mx6/imx-regs.h | 1 +
> arch/arm/include/asm/arch-mx6/sys_proto.h | 6 ++++++
> 3 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index b21bd03..29de624 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -62,6 +62,7 @@ u32 get_cpu_rev(void)
> struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
> u32 reg = readl(&anatop->digprog_sololite);
> u32 type = ((reg >> 16) & 0xff);
> + u32 major;
>
> if (type != MXC_CPU_MX6SL) {
> reg = readl(&anatop->digprog);
> @@ -79,8 +80,9 @@ u32 get_cpu_rev(void)
> }
>
> }
> + major = ((reg >> 8) & 0xff);
> reg &= 0xff; /* mx6 silicon revision */
> - return (type << 12) | (reg + 0x10);
> + return (type << 12) | (reg + (0x10 * (major + 1)));
> }
>
> /*
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 0d38d45..35a324c 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -312,6 +312,7 @@
> #define CHIP_REV_1_0 0x10
> #define CHIP_REV_1_2 0x12
> #define CHIP_REV_1_5 0x15
> +#define CHIP_REV_2_0 0x20
> #ifndef CONFIG_MX6SX
> #define IRAM_SIZE 0x00040000
> #else
> diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
> index 9c827c9..c1d9c6d 100644
> --- a/arch/arm/include/asm/arch-mx6/sys_proto.h
> +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
> @@ -2,6 +2,8 @@
> * (C) Copyright 2009
> * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
> *
> + * (C) Copyright 2009-2015 Freescale Semiconductor, Inc.
> + *
> * SPDX-License-Identifier: GPL-2.0+
> */
>

mmhhh..we have already discussed this topic, Copyright should not be
changed by small changes in a file.

> @@ -30,6 +32,10 @@ const char *get_imx_type(u32 imxtype);
> unsigned imx_ddr_size(void);
> void set_chipselect_size(int const);
>
> +#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
> + is_cpu_type(MXC_CPU_MX6D)) && \
> + (is_soc_rev(CHIP_REV_2_0) >= 0))
> +

As "insider" you could better explain me: it looks like there will be
not a Quad/Dual with an increased chip revision. The new chip revision
for i.MX6 is really the QP (P=perfect, as I see some workaround can be
removed !)

Is it correct ? Else this conflicts if a 6Q with a revision > 2 will be
released.

Best regards,
Stefano Babic

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