[U-Boot] [PATCH 7/8] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support

Peng Fan
2015-06-10T08:06:42Z

1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.

Build target: mx6qpsabreauto_config

U-Boot 2015.07-rc2-00008-g594f506 (Jun 10 2015 - 16:01:36 +0800)

Boot Log:
CPU: Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz)
CPU: Automotive temperature grade (-40C to 125C) at 36C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C: ready
DRAM: 2 GiB
PMIC: PFUZE100 ID=0x10
Flash: 32 MiB
NAND: 4096 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment

No panel detected: default to HDMI
Display: HDMI (1024x768)
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Error: FEC address not set.

Hit any key to stop autoboot: 0

Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
board/freescale/mx6qsabreauto/mx6qp.cfg | 158 ++++++++++++++++++++++++++
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 32 +++++-
configs/mx6qpsabreauto_defconfig | 5 +
include/configs/mx6qsabreauto.h | 5 +-
4 files changed, 194 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg
create mode 100644 configs/mx6qpsabreauto_defconfig

diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg b/board/freescale/mx6qsabreauto/mx6qp.cfg
new file mode 100644
index 0000000..5d55bcc
--- /dev/null
+++ b/board/freescale/mx6qsabreauto/mx6qp.cfg
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand: flash_offset: 0x0400
+ * sata: flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM sd
+#endif
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6qsabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF 0x2000
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001b001e
+DATA 4 0x021b0810 0x002e0029
+DATA 4 0x021b480c 0x001b002a
+DATA 4 0x021b4810 0x0019002c
+DATA 4 0x021b083c 0x43240334
+DATA 4 0x021b0840 0x0324031a
+DATA 4 0x021b483c 0x43340344
+DATA 4 0x021b4840 0x03280276
+DATA 4 0x021b0848 0x44383A3E
+DATA 4 0x021b4848 0x3C3C3846
+DATA 4 0x021b0850 0x2e303230
+DATA 4 0x021b4850 0x38283E34
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x898E7955
+DATA 4 0x021b0010 0xFF328F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008E1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0400 0x12420000
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x00bb0008 0x00000004
+DATA 4 0x00bb000c 0x2891E41A
+DATA 4 0x00bb0038 0x00000564
+DATA 4 0x00bb0014 0x00000040
+DATA 4 0x00bb0028 0x00000020
+DATA 4 0x00bb002c 0x00000020
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0xFFFFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, 0x020e0018, 0x77177717
+DATA 4, 0x020e001c, 0x77177717
+#endif
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index b76e4eb..83e34c6 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -354,9 +354,27 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}

+static int setup_fec(void)
+{
+ int ret;
+
+#ifdef CONFIG_MX6QP
+ imx_iomux_set_gpr_register(5, 9, 1, 1);
+#else
+ imx_iomux_set_gpr_register(1, 21, 1, 1);
+#endif
+
+ ret = enable_fec_anatop_clock(ENET_125MHZ);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
+ setup_fec();

return cpu_eth_init(bis);
}
@@ -495,17 +513,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
int power_init_board(void)
{
struct pmic *p;
- unsigned int ret;
+ unsigned int value;

p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;

- ret = pfuze_mode_init(p, APS_PFM);
- if (ret < 0)
- return ret;
+ if (is_mx6dqp()) {
+ /* set SW2 staby volatage 0.975V*/
+ pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+ value &= ~0x3f;
+ value |= 0x17;
+ pmic_reg_write(p, PFUZE100_SW2STBY, value);
+ }

- return 0;
+ return pfuze_mode_init(p, APS_PFM);
}

#ifdef CONFIG_CMD_BMODE
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
new file mode 100644
index 0000000..e0b717a
--- /dev/null
+++ b/configs/mx6qpsabreauto_defconfig
@@ -0,0 +1,5 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6QP"
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_NET=y
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 2260344..6ac64e6 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -12,7 +12,10 @@
#define CONFIG_MACH_TYPE 3529
#define CONFIG_MXC_UART_BASE UART4_BASE
#define CONFIG_CONSOLE_DEV "ttymxc3"
-#if defined CONFIG_MX6Q
+
+#if defined CONFIG_MX6QP
+#define CONFIG_DEFAULT_FDT_FILE "imx6qp-sabreauto.dtb"
+#elif defined CONFIG_MX6Q
#define CONFIG_DEFAULT_FDT_FILE "imx6q-sabreauto.dtb"
#elif defined CONFIG_MX6DL
#define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabreauto.dtb"
--
1.8.4