From: Pavel Machek <pavel@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCHv4 1/3] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
Date: Mon, 22 Jun 2015 12:56:15 +0200 [thread overview]
Message-ID: <20150622105614.GA19027@amd> (raw)
In-Reply-To: <1434965918.2855.3.camel@clsee-VirtualBox.altera.com>
Hi!
> > > Comment what kind of errata this is working around?
> > >
> >
> > I'll have to ask around.
>
>
> It is to workaround the computational of SDRAM rows. The info is then
> used to calculate the SDRAM size. By doing this, we can remove from
> hardcoding the SDRAM size into the code. More info at
> https://github.com/altera-opensource/u-boot-socfpga/commit/93815696dce132ff8abc4ab2f4c195339ff821a0. Hope this explains.
>
Ok, can you add a comment into the sources explaining what is going
on?
Normally, chip errata are documented somewhere and have numbers, that
would be best thing to link there. (But the github link is also better
than nothing...)
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
next prev parent reply other threads:[~2015-06-22 10:56 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-03 3:52 [U-Boot] [PATCHv4 0/3] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA dinguyen at opensource.altera.com
2015-06-03 3:52 ` [U-Boot] [PATCHv4 1/3] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller dinguyen at opensource.altera.com
2015-06-09 11:55 ` Pavel Machek
2015-06-09 12:58 ` Wolfgang Denk
2015-06-09 15:51 ` Dinh Nguyen
2015-06-22 9:38 ` Chin Liang See
2015-06-22 10:56 ` Pavel Machek [this message]
2015-06-03 3:52 ` [U-Boot] [PATCHv4 2/3] driver/ddr/altera: Add the sdram calibration portion dinguyen at opensource.altera.com
2015-06-09 12:21 ` Pavel Machek
2015-06-03 3:52 ` [U-Boot] [PATCHv4 3/3] arm: socfpga: enable the Altera SDRAM controller driver dinguyen at opensource.altera.com
2015-06-09 12:25 ` Pavel Machek
2015-06-26 16:43 ` [U-Boot] [PATCHv4 0/3] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA Marek Vasut
2015-06-26 20:01 ` Marek Vasut
2015-07-12 19:50 ` Marek Vasut
2015-07-17 19:58 ` Dinh Nguyen
2015-07-17 20:22 ` Marek Vasut
2015-07-18 23:51 ` Marek Vasut
2015-07-20 13:40 ` Dinh Nguyen
2015-07-20 18:36 ` Marek Vasut
2015-07-20 19:31 ` Dinh Nguyen
2015-07-20 19:40 ` Marek Vasut
2015-07-21 22:46 ` Dinh Nguyen
2015-07-22 3:24 ` Marek Vasut
2015-07-23 18:29 ` Dinh Nguyen
2015-07-24 3:57 ` Marek Vasut
2015-07-22 8:27 ` Dinh Nguyen
2015-07-22 9:00 ` Marek Vasut
2015-07-22 12:57 ` Dinh Nguyen
2015-07-22 13:01 ` Marek Vasut
2015-07-23 4:03 ` Dinh Nguyen
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