* [U-Boot] [PATCH 1/8] drivers:usb:dwc3: Add DWC3 controller driver support
2015-05-29 9:17 [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code Ramneek Mehresh
@ 2015-05-29 9:17 ` Ramneek Mehresh
2015-06-03 14:09 ` Tom Rini
2015-05-29 9:17 ` [U-Boot] [PATCH 2/8] usb:xhci:exynos: Remove common dwc3 drv functions calls Ramneek Mehresh
` (7 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Ramneek Mehresh @ 2015-05-29 9:17 UTC (permalink / raw)
To: u-boot
Add support for DWC3 XHCI controller driver
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
drivers/usb/host/Makefile | 1 +
drivers/usb/host/xhci-dwc3.c | 91 ++++++++++++++++++++++++++++++++++++++++++++
include/linux/usb/dwc3.h | 6 +++
3 files changed, 98 insertions(+)
create mode 100644 drivers/usb/host/xhci-dwc3.c
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 4d35d3e..310d979 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
new file mode 100644
index 0000000..67147cb
--- /dev/null
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * DWC3 controller driver
+ *
+ * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/usb/dwc3.h>
+
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+ clrsetbits_le32(&dwc3_reg->g_ctl,
+ DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+ DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+void dwc3_phy_reset(struct dwc3 *dwc3_reg)
+{
+ /* Assert USB3 PHY reset */
+ setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(100);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+ /* Before Resetting PHY, put Core in Reset */
+ setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+ /* reset USB3 phy - if required */
+ dwc3_phy_reset(dwc3_reg);
+
+ /* After PHYs are stable we can take Core out of reset state */
+ clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+ u32 reg;
+ u32 revision;
+ unsigned int dwc3_hwparams1;
+
+ revision = readl(&dwc3_reg->g_snpsid);
+ /* This should read as U3 followed by revision number */
+ if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
+ puts("this is not a DesignWare USB3 DRD Core\n");
+ return -1;
+ }
+
+ dwc3_core_soft_reset(dwc3_reg);
+
+ dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
+
+ reg = readl(&dwc3_reg->g_ctl);
+ reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+ reg &= ~DWC3_GCTL_DISSCRAMBLE;
+ switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+ case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+ reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+ break;
+ default:
+ debug("No power optimization available\n");
+ }
+
+ /*
+ * WORKAROUND: DWC3 revisions <1.90a have a bug
+ * where the device can fail to connect@SuperSpeed
+ * and falls back to high-speed mode which causes
+ * the device to enter a Connect/Disconnect loop
+ */
+ if ((revision & DWC3_REVISION_MASK) < 0x190a)
+ reg |= DWC3_GCTL_U2RSTECN;
+
+ writel(reg, &dwc3_reg->g_ctl);
+
+ return 0;
+}
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 7edc760..ba7f314 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -191,4 +191,10 @@ struct dwc3 { /* offset: 0xC100 */
#define DWC3_DCTL_CSFTRST (1 << 30)
#define DWC3_DCTL_LSFTRST (1 << 29)
+#ifdef CONFIG_USB_XHCI_DWC3
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
+int dwc3_core_init(struct dwc3 *dwc3_reg);
+void usb_phy_reset(struct dwc3 *dwc3_reg);
+#endif
#endif /* __DWC3_H_ */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH 2/8] usb:xhci:exynos: Remove common dwc3 drv functions calls
2015-05-29 9:17 [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code Ramneek Mehresh
2015-05-29 9:17 ` [U-Boot] [PATCH 1/8] drivers:usb:dwc3: Add DWC3 controller driver support Ramneek Mehresh
@ 2015-05-29 9:17 ` Ramneek Mehresh
2015-06-03 14:09 ` Tom Rini
2015-05-29 9:17 ` [U-Boot] [PATCH 3/8] usb:xhci:omap: " Ramneek Mehresh
` (6 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Ramneek Mehresh @ 2015-05-29 9:17 UTC (permalink / raw)
To: u-boot
Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
drivers/usb/host/xhci-exynos5.c | 78 ----------------------------------------
include/configs/exynos5-common.h | 1 +
2 files changed, 1 insertion(+), 78 deletions(-)
diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c
index a27a796..251885b 100644
--- a/drivers/usb/host/xhci-exynos5.c
+++ b/drivers/usb/host/xhci-exynos5.c
@@ -179,84 +179,6 @@ static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy)
set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE);
}
-static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
-{
- clrsetbits_le32(&dwc3_reg->g_ctl,
- DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
- DWC3_GCTL_PRTCAPDIR(mode));
-}
-
-static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
-{
- /* Before Resetting PHY, put Core in Reset */
- setbits_le32(&dwc3_reg->g_ctl,
- DWC3_GCTL_CORESOFTRESET);
-
- /* Assert USB3 PHY reset */
- setbits_le32(&dwc3_reg->g_usb3pipectl[0],
- DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Assert USB2 PHY reset */
- setbits_le32(&dwc3_reg->g_usb2phycfg,
- DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- mdelay(100);
-
- /* Clear USB3 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb3pipectl[0],
- DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Clear USB2 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb2phycfg,
- DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- /* After PHYs are stable we can take Core out of reset state */
- clrbits_le32(&dwc3_reg->g_ctl,
- DWC3_GCTL_CORESOFTRESET);
-}
-
-static int dwc3_core_init(struct dwc3 *dwc3_reg)
-{
- u32 reg;
- u32 revision;
- unsigned int dwc3_hwparams1;
-
- revision = readl(&dwc3_reg->g_snpsid);
- /* This should read as U3 followed by revision number */
- if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
- puts("this is not a DesignWare USB3 DRD Core\n");
- return -EINVAL;
- }
-
- dwc3_core_soft_reset(dwc3_reg);
-
- dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
-
- reg = readl(&dwc3_reg->g_ctl);
- reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
- reg &= ~DWC3_GCTL_DISSCRAMBLE;
- switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
- case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
- reg &= ~DWC3_GCTL_DSBLCLKGTNG;
- break;
- default:
- debug("No power optimization available\n");
- }
-
- /*
- * WORKAROUND: DWC3 revisions <1.90a have a bug
- * where the device can fail to connect@SuperSpeed
- * and falls back to high-speed mode which causes
- * the device to enter a Connect/Disconnect loop
- */
- if ((revision & DWC3_REVISION_MASK) < 0x190a)
- reg |= DWC3_GCTL_U2RSTECN;
-
- writel(reg, &dwc3_reg->g_ctl);
-
- return 0;
-}
-
static int exynos_xhci_core_init(struct exynos_xhci *exynos)
{
int ret;
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 5476248..e04dec7 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -182,6 +182,7 @@
/* USB */
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
+#define CONFIG_USB_XHCI_DWC3
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
--
1.8.3.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH 3/8] usb:xhci:omap: Remove common dwc3 drv functions calls
2015-05-29 9:17 [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code Ramneek Mehresh
2015-05-29 9:17 ` [U-Boot] [PATCH 1/8] drivers:usb:dwc3: Add DWC3 controller driver support Ramneek Mehresh
2015-05-29 9:17 ` [U-Boot] [PATCH 2/8] usb:xhci:exynos: Remove common dwc3 drv functions calls Ramneek Mehresh
@ 2015-05-29 9:17 ` Ramneek Mehresh
2015-06-03 14:10 ` Tom Rini
2015-05-29 9:17 ` [U-Boot] [PATCH 4/8] usb:xhci:keystone: " Ramneek Mehresh
` (5 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Ramneek Mehresh @ 2015-05-29 9:17 UTC (permalink / raw)
To: u-boot
Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
drivers/usb/host/xhci-omap.c | 60 ------------------------------------------
drivers/usb/phy/omap_usb_phy.c | 18 -------------
include/configs/am43xx_evm.h | 1 +
include/configs/beagle_x15.h | 1 +
include/configs/dra7xx_evm.h | 1 +
5 files changed, 3 insertions(+), 78 deletions(-)
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index 912b2bd..3a55208 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -34,66 +34,6 @@ inline int __board_usb_init(int index, enum usb_init_type init)
int board_usb_init(int index, enum usb_init_type init)
__attribute__((weak, alias("__board_usb_init")));
-static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
-{
- clrsetbits_le32(&dwc3_reg->g_ctl,
- DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
- DWC3_GCTL_PRTCAPDIR(mode));
-}
-
-static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
-{
- /* Before Resetting PHY, put Core in Reset */
- setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
-
- omap_reset_usb_phy(dwc3_reg);
-
- /* After PHYs are stable we can take Core out of reset state */
- clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
-}
-
-static int dwc3_core_init(struct dwc3 *dwc3_reg)
-{
- u32 reg;
- u32 revision;
- unsigned int dwc3_hwparams1;
-
- revision = readl(&dwc3_reg->g_snpsid);
- /* This should read as U3 followed by revision number */
- if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
- puts("this is not a DesignWare USB3 DRD Core\n");
- return -1;
- }
-
- dwc3_core_soft_reset(dwc3_reg);
-
- dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
-
- reg = readl(&dwc3_reg->g_ctl);
- reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
- reg &= ~DWC3_GCTL_DISSCRAMBLE;
- switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
- case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
- reg &= ~DWC3_GCTL_DSBLCLKGTNG;
- break;
- default:
- debug("No power optimization available\n");
- }
-
- /*
- * WORKAROUND: DWC3 revisions <1.90a have a bug
- * where the device can fail to connect@SuperSpeed
- * and falls back to high-speed mode which causes
- * the device to enter a Connect/Disconnect loop
- */
- if ((revision & DWC3_REVISION_MASK) < 0x190a)
- reg |= DWC3_GCTL_U2RSTECN;
-
- writel(reg, &dwc3_reg->g_ctl);
-
- return 0;
-}
-
static int omap_xhci_core_init(struct omap_xhci *omap)
{
int ret = 0;
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index 63d9301..f9069c7 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -223,24 +223,6 @@ void usb_phy_power(int on)
}
#endif /* CONFIG_AM437X_USB2PHY2_HOST */
-void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
-{
- /* Assert USB3 PHY reset */
- setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Assert USB2 PHY reset */
- setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- mdelay(100);
-
- /* Clear USB3 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Clear USB2 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
-}
-
void omap_enable_phy(struct omap_xhci *omap)
{
#ifdef CONFIG_OMAP_USB2PHY2_HOST
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 331fdac..276aee4 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -102,6 +102,7 @@
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h
index 4aa8550..f350d79 100644
--- a/include/configs/beagle_x15.h
+++ b/include/configs/beagle_x15.h
@@ -66,6 +66,7 @@
/* USB xHCI HOST */
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index d79612b..c690795 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -173,6 +173,7 @@
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
--
1.8.3.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH 4/8] usb:xhci:keystone: Remove common dwc3 drv functions calls
2015-05-29 9:17 [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code Ramneek Mehresh
` (2 preceding siblings ...)
2015-05-29 9:17 ` [U-Boot] [PATCH 3/8] usb:xhci:omap: " Ramneek Mehresh
@ 2015-05-29 9:17 ` Ramneek Mehresh
2015-06-03 14:09 ` Tom Rini
2015-05-29 9:17 ` [U-Boot] [PATCH 5/8] drivers:usb:fsl: Add XHCI driver support Ramneek Mehresh
` (4 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Ramneek Mehresh @ 2015-05-29 9:17 UTC (permalink / raw)
To: u-boot
Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
drivers/usb/host/xhci-keystone.c | 88 ----------------------------------------
include/configs/ks2_evm.h | 1 +
2 files changed, 1 insertion(+), 88 deletions(-)
diff --git a/drivers/usb/host/xhci-keystone.c b/drivers/usb/host/xhci-keystone.c
index 05d338f..924fb76 100644
--- a/drivers/usb/host/xhci-keystone.c
+++ b/drivers/usb/host/xhci-keystone.c
@@ -68,94 +68,6 @@ static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy)
writel(val, &phy->phy_clock);
}
-static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
-{
- clrsetbits_le32(&dwc3_reg->g_ctl,
- DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
- DWC3_GCTL_PRTCAPDIR(mode));
-}
-
-static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
-{
- /* Before Resetting PHY, put Core in Reset */
- setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
-
- /* Assert USB3 PHY reset */
- setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Assert USB2 PHY reset */
- setbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- mdelay(100);
-
- /* Clear USB3 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Clear USB2 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- /* After PHYs are stable we can take Core out of reset state */
- clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
-}
-
-static int dwc3_core_init(struct dwc3 *dwc3_reg)
-{
- u32 revision, val;
- unsigned long t_rst;
- unsigned int dwc3_hwparams1;
-
- revision = readl(&dwc3_reg->g_snpsid);
- /* This should read as U3 followed by revision number */
- if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
- puts("this is not a DesignWare USB3 DRD Core\n");
- return -EINVAL;
- }
-
- /* issue device SoftReset too */
- writel(DWC3_DCTL_CSFTRST, &dwc3_reg->d_ctl);
-
- t_rst = get_timer(0);
- do {
- val = readl(&dwc3_reg->d_ctl);
- if (!(val & DWC3_DCTL_CSFTRST))
- break;
- WATCHDOG_RESET();
- } while (get_timer(t_rst) < 500);
-
- if (val & DWC3_DCTL_CSFTRST) {
- debug("Reset timed out\n");
- return -2;
- }
-
- dwc3_core_soft_reset(dwc3_reg);
-
- dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
-
- val = readl(&dwc3_reg->g_ctl);
- val &= ~DWC3_GCTL_SCALEDOWN_MASK;
- val &= ~DWC3_GCTL_DISSCRAMBLE;
- switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
- case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
- val &= ~DWC3_GCTL_DSBLCLKGTNG;
- break;
- default:
- printf("No power optimization available\n");
- }
-
- /*
- * WORKAROUND: DWC3 revisions <1.90a have a bug
- * where the device can fail to connect@SuperSpeed
- * and falls back to high-speed mode which causes
- * the device to enter a Connect/Disconnect loop
- */
- if ((revision & DWC3_REVISION_MASK) < 0x190a)
- val |= DWC3_GCTL_U2RSTECN;
-
- writel(val, &dwc3_reg->g_ctl);
-
- return 0;
-}
-
static int keystone_xhci_core_init(struct dwc3 *dwc3_reg)
{
int ret;
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 42280ca..58730b2 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -197,6 +197,7 @@
/* USB Configuration */
#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
--
1.8.3.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH 5/8] drivers:usb:fsl: Add XHCI driver support
2015-05-29 9:17 [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code Ramneek Mehresh
` (3 preceding siblings ...)
2015-05-29 9:17 ` [U-Boot] [PATCH 4/8] usb:xhci:keystone: " Ramneek Mehresh
@ 2015-05-29 9:17 ` Ramneek Mehresh
2015-06-03 14:09 ` Tom Rini
2015-05-29 9:17 ` [U-Boot] [PATCH 6/8] arch:arm:fsl: Add XHCI support for LS1021A Ramneek Mehresh
` (3 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Ramneek Mehresh @ 2015-05-29 9:17 UTC (permalink / raw)
To: u-boot
From: ramneek mehresh <ramneek.mehresh@freescale.com>
Add xhci driver support for all FSL socs
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
drivers/usb/host/Makefile | 1 +
drivers/usb/host/xhci-fsl.c | 109 +++++++++++++++++++++++++++++++++++++++++++
include/linux/usb/xhci-fsl.h | 54 +++++++++++++++++++++
3 files changed, 164 insertions(+)
create mode 100644 drivers/usb/host/xhci-fsl.c
create mode 100644 include/linux/usb/xhci-fsl.h
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 310d979..6cc3bbd 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
new file mode 100644
index 0000000..f624c90
--- /dev/null
+++ b/drivers/usb/host/xhci-fsl.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm-generic/errno.h>
+#include <asm/arch-ls102xa/immap_ls102xa.h>
+#include <linux/compat.h>
+#include <linux/usb/xhci-fsl.h>
+#include <linux/usb/dwc3.h>
+#include "xhci.h"
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fsl_xhci fsl_xhci;
+unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
+
+__weak int __board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_phy_reset(struct dwc3 *dwc3_reg)
+{
+ /* Assert USB3 PHY reset */
+ setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(200);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
+{
+ int ret = 0;
+
+ ret = dwc3_core_init(fsl_xhci->dwc3_reg);
+ if (ret) {
+ debug("%s:failed to initialize core\n", __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
+{
+ /*
+ * Currently fsl socs do not support PHY shutdown from
+ * sw. But this support may be added in future socs.
+ */
+ return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ struct fsl_xhci *ctx = &fsl_xhci;
+ int ret = 0;
+
+ ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
+ ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts("Failed to initialize board for USB\n");
+ return ret;
+ }
+
+ ret = fsl_xhci_core_init(ctx);
+ if (ret < 0) {
+ puts("Failed to initialize xhci\n");
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)ctx->hcd;
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+ debug("fsl-xhci: init hccr %x and hcor %x hc_length %d\n",
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct fsl_xhci *ctx = &fsl_xhci;
+
+ fsl_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
new file mode 100644
index 0000000..8eaab2c
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_FSL_H_
+#define _ASM_ARCH_XHCI_FSL_H_
+
+/* Default to the FSL XHCI defines */
+#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
+#define USB3_PHY_RX_POWERON BIT(14)
+#define USB3_PHY_TX_POWERON BIT(15)
+#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT 14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET BIT(17)
+#define USBOTGSS_DMADISABLE BIT(16)
+#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
+#define USBOTGSS_STANDBYMODE_SMRT BIT(5)
+#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
+#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
+#define USBOTGSS_IDLEMODE_SMRT BIT(3)
+#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
+
+/* USBOTGSS_IRQENABLE_SET_0 bit */
+#define USBOTGSS_COREIRQ_EN BIT(1)
+
+/* USBOTGSS_IRQENABLE_SET_1 bits */
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5)
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13)
+#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
+#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
+
+struct fsl_xhci {
+ struct xhci_hccr *hcd;
+ struct dwc3 *dwc3_reg;
+};
+
+#endif /* _ASM_ARCH_XHCI_FSL_H_ */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH 6/8] arch:arm:fsl: Add XHCI support for LS1021A
2015-05-29 9:17 [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code Ramneek Mehresh
` (4 preceding siblings ...)
2015-05-29 9:17 ` [U-Boot] [PATCH 5/8] drivers:usb:fsl: Add XHCI driver support Ramneek Mehresh
@ 2015-05-29 9:17 ` Ramneek Mehresh
2015-06-03 14:09 ` Tom Rini
2015-05-29 9:17 ` [U-Boot] [PATCH 7/8] include:configs:ls1021atwr: Enable USB IP support Ramneek Mehresh
` (2 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Ramneek Mehresh @ 2015-05-29 9:17 UTC (permalink / raw)
To: u-boot
From: ramneek mehresh <ramneek.mehresh@freescale.com>
Add base register address information for USB
XHCI controller on LS1021A
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 4dc528b..c55cdef 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -35,6 +35,7 @@
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
+#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index ee547fb..8e5fcdc 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -395,4 +395,14 @@ struct ccsr_cci400 {
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x10000 - 0xe004];
};
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE 0x3100000
+#define FSL_OCP1_SCP_BASE 0x4a084c00
+#define FSL_OTG_WRAPPER_BASE 0x4A020000
+
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+ CONFIG_SYS_FSL_XHCI_USB2_ADDR}
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH 7/8] include:configs:ls1021atwr: Enable USB IP support
2015-05-29 9:17 [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code Ramneek Mehresh
` (5 preceding siblings ...)
2015-05-29 9:17 ` [U-Boot] [PATCH 6/8] arch:arm:fsl: Add XHCI support for LS1021A Ramneek Mehresh
@ 2015-05-29 9:17 ` Ramneek Mehresh
2015-06-03 14:10 ` Tom Rini
2015-05-29 9:17 ` [U-Boot] [PATCH 8/8] include:configs:ls1021aqds: " Ramneek Mehresh
2015-06-07 13:32 ` [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code Marek Vasut
8 siblings, 1 reply; 19+ messages in thread
From: Ramneek Mehresh @ 2015-05-29 9:17 UTC (permalink / raw)
To: u-boot
From: ramneek mehresh <ramneek.mehresh@freescale.com>
Enable USB IP support for both EHCI and XHCI for
ls1021atwr platform
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
include/configs/ls1021atwr.h | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 8ea428e..f2dca5e 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -28,6 +28,44 @@
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/*
+ * USB
+ */
+
+/*
+ * EHCI Support - disbaled by default as
+ * there is no signal coming out of soc on
+ * this board for this controller. However,
+ * the silicon still has this controller,
+ * and anyone can use this controller by
+ * taking signals out on their board.
+ */
+
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/* XHCI Support - enabled by default */
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
* Generic Timer Definitions
*/
#define GENERIC_TIMER_CLK 12500000
--
1.8.3.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH 8/8] include:configs:ls1021aqds: Enable USB IP support
2015-05-29 9:17 [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code Ramneek Mehresh
` (6 preceding siblings ...)
2015-05-29 9:17 ` [U-Boot] [PATCH 7/8] include:configs:ls1021atwr: Enable USB IP support Ramneek Mehresh
@ 2015-05-29 9:17 ` Ramneek Mehresh
2015-06-03 14:09 ` Tom Rini
2015-06-07 13:32 ` [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code Marek Vasut
8 siblings, 1 reply; 19+ messages in thread
From: Ramneek Mehresh @ 2015-05-29 9:17 UTC (permalink / raw)
To: u-boot
From: ramneek mehresh <ramneek.mehresh@freescale.com>
Enable USB IP support for both EHCI and XHCI for
ls1021aqds platform
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
include/configs/ls1021aqds.h | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 1a41a2f..095c32b 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -424,19 +424,31 @@ unsigned long get_board_ddr_clk(void);
/*
* USB
*/
-#define CONFIG_HAS_FSL_DR_USB
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
-#ifdef CONFIG_USB_EHCI
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_CMD_EXT2
#endif
-#endif
/*
* Video
--
1.8.3.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code
2015-05-29 9:17 [U-Boot] [PATCH 0/8] usb:xhci:dwc3: Add dwc3 drv code Ramneek Mehresh
` (7 preceding siblings ...)
2015-05-29 9:17 ` [U-Boot] [PATCH 8/8] include:configs:ls1021aqds: " Ramneek Mehresh
@ 2015-06-07 13:32 ` Marek Vasut
[not found] ` <SN1PR0301MB1583C4E922C45EE033AFEA2EE0A10@SN1PR0301MB1583.namprd03.prod.outlook.com>
8 siblings, 1 reply; 19+ messages in thread
From: Marek Vasut @ 2015-06-07 13:32 UTC (permalink / raw)
To: u-boot
On Friday, May 29, 2015 at 11:17:14 AM, Ramneek Mehresh wrote:
> A lot of dwc3 code has been duplicated in various xhci
> drivers. Hence, to minimize this duplication, a new
> dwc3 file is written that provides common APIs for
> all other drivers.
>
> First four patches introduce dwc3 file, and necessary
> changes are made in other drivers for this new drv.
> I would request all platform/driver owners to please help
> me in testng these changes on their respective platforms.
>
> Last four patches are freescale layerscape la1021aqds/
> ls1021atwr platform specific.
>
> Ramneek Mehresh (4):
> drivers:usb:dwc3: Add DWC3 controller driver support
Please put space after : , always.
> usb:xhci:exynos: Remove common dwc3 drv functions calls
> usb:xhci:omap: Remove common dwc3 drv functions calls
> usb:xhci:keystone: Remove common dwc3 drv functions calls
>
> ramneek mehresh (4):
It might be a good idea to crosscheck your name with your ID card ...
> drivers:usb:fsl: Add XHCI driver support
There's no such tag as "drivers:".
> arch:arm:fsl: Add XHCI support for LS1021A
> include:configs:ls1021atwr: Enable USB IP support
> include:configs:ls1021aqds: Enable USB IP support
The tag doesn't really describe path or anything, so just boardname
is fine in this case.
I fixed all those and applied to u-boot-usb/next .
Thanks
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 19+ messages in thread