[U-Boot] [PATCH v1 0/9] mvebu/a38x: Add MMC/SDIO, SATA/AHCI and USB/EHCI support

[U-Boot] [PATCH v1 0/9] mvebu/a38x: Add MMC/SDIO, SATA/AHCI and USB/EHCI support

[Stefan Roese]

This patch series adds support for the following interfaces on the
Marvell A38x Soc in mainline U-Boot:

- MMC/SDIO/SDHCI
- SATA/SCSI/AHCI
- USB/EHCI

Tested on Marvell Armada 38x DB-88F6820-GP eval board.

Thanks,
Stefan


Stefan Roese (9):
  mmc: sdhci: Use timer based timeout detection in sdhci_send_command()
  mmc: sdhci.c: Add config option to use a fixed buffer for transfers
  arm: mvebu: Add SDIO/SDHCI support for Armada A38x
  arm: mvebu: db-88f6820-gp: Add MMC/SDIO support
  block: ahci: Don't enable port interrupts
  arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38x
  arm: mvebu: db-88f6820-gp.h: Add SATA/SCSI (AHCI) support
  usb: Add EHCI support for Armada 38x (mvebu)
  arm: mvebu: db-88f6820-gp: Add USB/EHCI support

 arch/arm/mach-mvebu/cpu.c               | 66 +++++++++++++++++++++++++++++++++
 arch/arm/mach-mvebu/include/mach/cpu.h  |  2 +
 arch/arm/mach-mvebu/include/mach/gpio.h | 10 +++++
 arch/arm/mach-mvebu/include/mach/soc.h  |  3 ++
 drivers/block/ahci.c                    |  3 --
 drivers/mmc/sdhci.c                     | 25 ++++++++++---
 drivers/usb/host/ehci-marvell.c         | 36 ++++++++++++++++++
 include/configs/db-88f6820-gp.h         | 41 ++++++++++++++++++++
 8 files changed, 178 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/mach-mvebu/include/mach/gpio.h

-- 
2.4.5

[U-Boot] [PATCH v1 1/9] mmc: sdhci: Use timer based timeout detection in sdhci_send_command()

[Stefan Roese]

The loop counter based timeout detection does not work on the Armada
38x based board (DB-88F6820-GP). At least with dcache enabled a
timeout is detected. Without dcache enabled, the timeout does not
occur. Increasing the loop counter solves this issue. But a better
solution is to use a timer based timeout detection instead. This
patch now implements this timer based detection.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---

 drivers/mmc/sdhci.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 75556a3..f72536b 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -133,8 +133,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 	int trans_bytes = 0, is_aligned = 1;
 	u32 mask, flags, mode;
 	unsigned int time = 0, start_addr = 0;
-	unsigned int retry = 10000;
 	int mmc_dev = mmc->block_dev.dev;
+	unsigned start = get_timer(0);
 
 	/* Timeout unit - ms */
 	static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
@@ -222,15 +222,15 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 	flush_cache(start_addr, trans_bytes);
 #endif
 	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
+	start = get_timer(0);
 	do {
 		stat = sdhci_readl(host, SDHCI_INT_STATUS);
 		if (stat & SDHCI_INT_ERROR)
 			break;
-		if (--retry == 0)
-			break;
-	} while ((stat & mask) != mask);
+	} while (((stat & mask) != mask) &&
+		 (get_timer(start) < CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT));
 
-	if (retry == 0) {
+	if (get_timer(start) >= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT) {
 		if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
 			return 0;
 		else {
-- 
2.4.5

[U-Boot] [PATCH v1 2/9] mmc: sdhci.c: Add config option to use a fixed buffer for transfers

[Stefan Roese]

While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the
following problem occured. The SPL runs in internal SRAM which is
the L2 cache locked to memory. When the MMC buffers now are located
on the stack (or bss), the SDIO controller (SDHCI) can't write into
this L2 cache memory.

This patch introduces a method to use a fixed buffer that will be
used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER.
This way, the board can use this buffer address located in SDRAM
for all transfers. This solves this SPL problem on the A38x and
should only be used in the SPL U-Boot version.

Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---

 drivers/mmc/sdhci.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index f72536b..d89e302 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -13,7 +13,11 @@
 #include <mmc.h>
 #include <sdhci.h>
 
+#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
+void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
+#else
 void *aligned_buffer;
+#endif
 
 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 {
@@ -205,6 +209,17 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 				memcpy(aligned_buffer, data->src, trans_bytes);
 		}
 
+#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
+		/*
+		 * Always use this bounce-buffer when
+		 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
+		 */
+		is_aligned = 0;
+		start_addr = (unsigned long)aligned_buffer;
+		if (data->flags != MMC_DATA_READ)
+			memcpy(aligned_buffer, data->src, trans_bytes);
+#endif
+
 		sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 		mode |= SDHCI_TRNS_DMA;
 #endif
-- 
2.4.5

[U-Boot] [PATCH v1 3/9] arm: mvebu: Add SDIO/SDHCI support for Armada A38x

[Stefan Roese]

Armada A38x implements an SDHCI compatible SDIO controller. This patch
enables the Marvell driver to support this SoC. And enables the
SDIO controller if selected by the board configuration.

Tested on Marvell DB-88F6820-GP board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---

 arch/arm/mach-mvebu/cpu.c               | 11 +++++++++++
 arch/arm/mach-mvebu/include/mach/cpu.h  |  2 ++
 arch/arm/mach-mvebu/include/mach/gpio.h | 10 ++++++++++
 arch/arm/mach-mvebu/include/mach/soc.h  |  1 +
 4 files changed, 24 insertions(+)
 create mode 100644 arch/arm/mach-mvebu/include/mach/gpio.h

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 0121db8..531d0fb 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -10,6 +10,7 @@
 #include <asm/pl310.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
+#include <sdhci.h>
 
 #define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))
 #define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))
@@ -245,6 +246,16 @@ int cpu_eth_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MV_SDHCI
+int board_mmc_init(bd_t *bis)
+{
+	mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
+		    SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
+
+	return 0;
+}
+#endif
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index 3b48460..4bdb633 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -114,6 +114,8 @@ void mvebu_sdram_size_adjust(enum memory_bank bank);
 int mvebu_mbus_probe(struct mbus_win windows[], int count);
 int mvebu_soc_family(void);
 
+int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
 /*
  * Highspeed SERDES PHY config init, ported from bin_hdr
  * to mainline U-Boot
diff --git a/arch/arm/mach-mvebu/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h
new file mode 100644
index 0000000..09e3c50
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/gpio.h
@@ -0,0 +1,10 @@
+/*
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __MACH_MVEBU_GPIO_H
+#define __MACH_MVEBU_GPIO_H
+
+/* Empty file - sdhci requires this. */
+
+#endif
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 0a9307c..1aeec27 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -51,6 +51,7 @@
 #define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
 #define MVEBU_EGIGA0_BASE	(MVEBU_REGISTER(0x70000))
 #define MVEBU_EGIGA1_BASE	(MVEBU_REGISTER(0x74000))
+#define MVEBU_SDIO_BASE		(MVEBU_REGISTER(0xd8000))
 
 #define SDRAM_MAX_CS		4
 #define SDRAM_ADDR_MASK		0xFF000000
-- 
2.4.5

[U-Boot] [PATCH v1 4/9] arm: mvebu: db-88f6820-gp: Add MMC/SDIO support

[Stefan Roese]

This patch adds MMC/SDIO support to the Marvell DB-88F6820-GP board
configuration. Including support for the common partitions and
filesystems.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---

 include/configs/db-88f6820-gp.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 24dbf6b..67cf748 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -29,7 +29,12 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
@@ -48,6 +53,23 @@
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
 #define CONFIG_SPI_FLASH_STMICRO
 
+/*
+ * SDIO/MMC Card Configuration
+ */
+#define CONFIG_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SDHCI
+#define CONFIG_MV_SDHCI
+#define CONFIG_SYS_MMC_BASE		MVEBU_SDIO_BASE
+
+/* Partition support */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
+
 /* Environment in SPI NOR flash */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
-- 
2.4.5

[U-Boot] [PATCH v1 5/9] block: ahci: Don't enable port interrupts

[Stefan Roese]

This patch changes the initialization of the AHCI controller to not
enable the default interrupts (DEF_PORT_IRQ). As interrupts are
not used in U-Boot in general, this should not break the common AHCI
driver operation.

This change is needed to support the Marvell Armada 38x AHCI
controller. With interrupts enabled, this results in timeouts in
ahci_device_data_io(). Not enabling these interrupts fixes this
problem and the common AHCI driver works fine.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---

 drivers/block/ahci.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 4fb846a..9bab0fc 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -299,9 +299,6 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
 
 		writel(1 << i, mmio + HOST_IRQ_STAT);
 
-		/* set irq mask (enables interrupts) */
-		writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
-
 		/* register linkup ports */
 		tmp = readl(port_mmio + PORT_SCR_STAT);
 		debug("SATA port %d status: 0x%x\n", i, tmp);
-- 
2.4.5

[U-Boot] [PATCH v1 6/9] arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38x

[Stefan Roese]

This patch adds support for the common AHCI controller on the Marvell
Armada 38x.

Tested on the Marvell DB-88F6820-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---

 arch/arm/mach-mvebu/cpu.c              | 55 ++++++++++++++++++++++++++++++++++
 arch/arm/mach-mvebu/include/mach/soc.h |  1 +
 include/configs/db-88f6820-gp.h        |  1 +
 3 files changed, 57 insertions(+)

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 531d0fb..9bc9f00 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -6,6 +6,8 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <ahci.h>
+#include <linux/mbus.h>
 #include <asm/io.h>
 #include <asm/pl310.h>
 #include <asm/arch/cpu.h>
@@ -256,6 +258,59 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_SCSI_AHCI_PLAT
+#define AHCI_VENDOR_SPECIFIC_0_ADDR	0xa0
+#define AHCI_VENDOR_SPECIFIC_0_DATA	0xa4
+
+#define AHCI_WINDOW_CTRL(win)		(0x60 + ((win) << 4))
+#define AHCI_WINDOW_BASE(win)		(0x64 + ((win) << 4))
+#define AHCI_WINDOW_SIZE(win)		(0x68 + ((win) << 4))
+
+static void ahci_mvebu_mbus_config(void __iomem *base)
+{
+	const struct mbus_dram_target_info *dram;
+	int i;
+
+	dram = mvebu_mbus_dram_info();
+
+	for (i = 0; i < 4; i++) {
+		writel(0, base + AHCI_WINDOW_CTRL(i));
+		writel(0, base + AHCI_WINDOW_BASE(i));
+		writel(0, base + AHCI_WINDOW_SIZE(i));
+	}
+
+	for (i = 0; i < dram->num_cs; i++) {
+		const struct mbus_dram_window *cs = dram->cs + i;
+
+		writel((cs->mbus_attr << 8) |
+		       (dram->mbus_dram_target_id << 4) | 1,
+		       base + AHCI_WINDOW_CTRL(i));
+		writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
+		writel(((cs->size - 1) & 0xffff0000),
+		       base + AHCI_WINDOW_SIZE(i));
+	}
+}
+
+static void ahci_mvebu_regret_option(void __iomem *base)
+{
+	/*
+	 * Enable the regret bit to allow the SATA unit to regret a
+	 * request that didn't receive an acknowlegde and avoid a
+	 * deadlock
+	 */
+	writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
+	writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
+}
+
+void scsi_init(void)
+{
+	printf("MVEBU SATA INIT\n");
+	ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
+	ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
+	ahci_init((void __iomem *)MVEBU_SATA0_BASE);
+}
+#endif
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 1aeec27..e6bfbc2 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -51,6 +51,7 @@
 #define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
 #define MVEBU_EGIGA0_BASE	(MVEBU_REGISTER(0x70000))
 #define MVEBU_EGIGA1_BASE	(MVEBU_REGISTER(0x74000))
+#define MVEBU_SATA0_BASE	(MVEBU_REGISTER(0xa8000))
 #define MVEBU_SDIO_BASE		(MVEBU_REGISTER(0xd8000))
 
 #define SDRAM_MAX_CS		4
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 67cf748..9ea1624 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -36,6 +36,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_SCSI
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_TFTPPUT
-- 
2.4.5

[U-Boot] [PATCH v1 7/9] arm: mvebu: db-88f6820-gp.h: Add SATA/SCSI (AHCI) support

[Stefan Roese]

Configure and enable the SATA/SCSI (AHCI) support for the Marvell
DB-88F6820-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---

 include/configs/db-88f6820-gp.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 9ea1624..5bdb29f 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -64,6 +64,17 @@
 #define CONFIG_MV_SDHCI
 #define CONFIG_SYS_MMC_BASE		MVEBU_SDIO_BASE
 
+/*
+ * SATA/SCSI/AHCI configuration
+ */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					 CONFIG_SYS_SCSI_MAX_LUN)
+
 /* Partition support */
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
-- 
2.4.5

[U-Boot] [PATCH v1 8/9] usb: Add EHCI support for Armada 38x (mvebu)

[Stefan Roese]

This patch adds USB EHCI host support for the common mvebu platform.
Including the Armada 38x.

Tested on DB-88F6280-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---

 arch/arm/mach-mvebu/include/mach/soc.h |  1 +
 drivers/usb/host/ehci-marvell.c        | 36 ++++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index e6bfbc2..1aaea67 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -49,6 +49,7 @@
 #define MVEBU_EGIGA2_BASE	(MVEBU_REGISTER(0x30000))
 #define MVEBU_EGIGA3_BASE	(MVEBU_REGISTER(0x34000))
 #define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
+#define MVEBU_USB20_BASE	(MVEBU_REGISTER(0x58000))
 #define MVEBU_EGIGA0_BASE	(MVEBU_REGISTER(0x70000))
 #define MVEBU_EGIGA1_BASE	(MVEBU_REGISTER(0x74000))
 #define MVEBU_SATA0_BASE	(MVEBU_REGISTER(0xa8000))
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 1a5fd6e..03c489c 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -10,6 +10,7 @@
 #include <asm/io.h>
 #include <usb.h>
 #include "ehci.h"
+#include <linux/mbus.h>
 #include <asm/arch/cpu.h>
 
 #if defined(CONFIG_KIRKWOOD)
@@ -30,6 +31,40 @@ DECLARE_GLOBAL_DATA_PTR;
 /*
  * USB 2.0 Bridge Address Decoding registers setup
  */
+#ifdef CONFIG_ARMADA_XP
+
+#define MVUSB0_BASE		MVEBU_USB20_BASE
+
+/*
+ * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
+ * to the common mvebu archticture including the mbus setup, this
+ * will be the only function needed to configure the access windows
+ */
+static void usb_brg_adrdec_setup(void)
+{
+	const struct mbus_dram_target_info *dram;
+	int i;
+
+	dram = mvebu_mbus_dram_info();
+
+	for (i = 0; i < 4; i++) {
+		wrl(USB_WINDOW_CTRL(i), 0);
+		wrl(USB_WINDOW_BASE(i), 0);
+	}
+
+	for (i = 0; i < dram->num_cs; i++) {
+		const struct mbus_dram_window *cs = dram->cs + i;
+
+		/* Write size, attributes and target id to control register */
+		wrl(USB_WINDOW_CTRL(i),
+		    ((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+		    (dram->mbus_dram_target_id << 4) | 1);
+
+		/* Write base address to base register */
+		wrl(USB_WINDOW_BASE(i), cs->base);
+	}
+}
+#else
 static void usb_brg_adrdec_setup(void)
 {
 	int i;
@@ -69,6 +104,7 @@ static void usb_brg_adrdec_setup(void)
 		wrl(USB_WINDOW_BASE(i), base);
 	}
 }
+#endif
 
 /*
  * Create the appropriate control structures to manage
-- 
2.4.5

[U-Boot] [PATCH v1 9/9] arm: mvebu: db-88f6820-gp: Add USB/EHCI support

[Stefan Roese]

This patch enabled the USB/EHCI support for the Marvell
DB-88F6820-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

---

 include/configs/db-88f6820-gp.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 5bdb29f..a429107 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -41,6 +41,7 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_TFTPPUT
 #define CONFIG_CMD_TIME
+#define CONFIG_CMD_USB
 
 /* I2C */
 #define CONFIG_SYS_I2C
@@ -82,6 +83,12 @@
 /* Additional FS support/configuration */
 #define CONFIG_SUPPORT_VFAT
 
+/* USB/EHCI configuration */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+
 /* Environment in SPI NOR flash */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
-- 
2.4.5

[U-Boot] [PATCH v1 8/9] usb: Add EHCI support for Armada 38x (mvebu)

[Marek Vasut]

On Monday, June 29, 2015 at 02:58:15 PM, Stefan Roese wrote:
> This patch adds USB EHCI host support for the common mvebu platform.
> Including the Armada 38x.
> 
> Tested on DB-88F6280-GP eval board.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Luka Perkov <luka.perkov@sartura.hr>

Reviewed-by: Marek Vasut <marex@denx.de>

[...]

> +static void usb_brg_adrdec_setup(void)
> +{
> +	const struct mbus_dram_target_info *dram;
> +	int i;
> +
> +	dram = mvebu_mbus_dram_info();
> +
> +	for (i = 0; i < 4; i++) {
> +		wrl(USB_WINDOW_CTRL(i), 0);
> +		wrl(USB_WINDOW_BASE(i), 0);
> +	}

These wrl() accessors are a bit weird, but maybe there's some
marvell magic behind this?

Best regards,
Marek Vasut

[U-Boot] [PATCH v1 5/9] block: ahci: Don't enable port interrupts

[Simon Glass]

On 29 June 2015 at 06:58, Stefan Roese <sr@denx.de> wrote:
> This patch changes the initialization of the AHCI controller to not
> enable the default interrupts (DEF_PORT_IRQ). As interrupts are
> not used in U-Boot in general, this should not break the common AHCI
> driver operation.
>
> This change is needed to support the Marvell Armada 38x AHCI
> controller. With interrupts enabled, this results in timeouts in
> ahci_device_data_io(). Not enabling these interrupts fixes this
> problem and the common AHCI driver works fine.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Hans de Goede <hdegoede@redhat.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Luka Perkov <luka.perkov@sartura.hr>
> ---
>
>  drivers/block/ahci.c | 3 ---
>  1 file changed, 3 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

>
> diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
> index 4fb846a..9bab0fc 100644
> --- a/drivers/block/ahci.c
> +++ b/drivers/block/ahci.c
> @@ -299,9 +299,6 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
>
>                 writel(1 << i, mmio + HOST_IRQ_STAT);
>
> -               /* set irq mask (enables interrupts) */
> -               writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
> -
>                 /* register linkup ports */
>                 tmp = readl(port_mmio + PORT_SCR_STAT);
>                 debug("SATA port %d status: 0x%x\n", i, tmp);
> --
> 2.4.5
>

[U-Boot] [PATCH v1 8/9] usb: Add EHCI support for Armada 38x (mvebu)

[Stefan Roese]

Hi Marek,

On 29.06.2015 17:22, Marek Vasut wrote:
> On Monday, June 29, 2015 at 02:58:15 PM, Stefan Roese wrote:
>> This patch adds USB EHCI host support for the common mvebu platform.
>> Including the Armada 38x.
>>
>> Tested on DB-88F6280-GP eval board.
>>
>> Signed-off-by: Stefan Roese <sr@denx.de>
>> Cc: Marek Vasut <marex@denx.de>
>> Cc: Luka Perkov <luka.perkov@sartura.hr>
>
> Reviewed-by: Marek Vasut <marex@denx.de>

Thanks.

> [...]
>
>> +static void usb_brg_adrdec_setup(void)
>> +{
>> +	const struct mbus_dram_target_info *dram;
>> +	int i;
>> +
>> +	dram = mvebu_mbus_dram_info();
>> +
>> +	for (i = 0; i < 4; i++) {
>> +		wrl(USB_WINDOW_CTRL(i), 0);
>> +		wrl(USB_WINDOW_BASE(i), 0);
>> +	}
>
> These wrl() accessors are a bit weird, but maybe there's some
> marvell magic behind this?

Not really. They are just adding the controller base address. Its used 
in the current driver code - so I just used it here as well.

I'll send a patch to remove these macros (move to readl/writel) once all 
this is in mainline.

Thanks,
Stefan

[U-Boot] [PATCH v1 8/9] usb: Add EHCI support for Armada 38x (mvebu)

[Marek Vasut]

On Thursday, July 02, 2015 at 01:03:33 PM, Stefan Roese wrote:
> Hi Marek,
> 
> On 29.06.2015 17:22, Marek Vasut wrote:
> > On Monday, June 29, 2015 at 02:58:15 PM, Stefan Roese wrote:
> >> This patch adds USB EHCI host support for the common mvebu platform.
> >> Including the Armada 38x.
> >> 
> >> Tested on DB-88F6280-GP eval board.
> >> 
> >> Signed-off-by: Stefan Roese <sr@denx.de>
> >> Cc: Marek Vasut <marex@denx.de>
> >> Cc: Luka Perkov <luka.perkov@sartura.hr>
> > 
> > Reviewed-by: Marek Vasut <marex@denx.de>
> 
> Thanks.
> 
> > [...]
> > 
> >> +static void usb_brg_adrdec_setup(void)
> >> +{
> >> +	const struct mbus_dram_target_info *dram;
> >> +	int i;
> >> +
> >> +	dram = mvebu_mbus_dram_info();
> >> +
> >> +	for (i = 0; i < 4; i++) {
> >> +		wrl(USB_WINDOW_CTRL(i), 0);
> >> +		wrl(USB_WINDOW_BASE(i), 0);
> >> +	}
> > 
> > These wrl() accessors are a bit weird, but maybe there's some
> > marvell magic behind this?
> 
> Not really. They are just adding the controller base address. Its used
> in the current driver code - so I just used it here as well.
> 
> I'll send a patch to remove these macros (move to readl/writel) once all
> this is in mainline.

I guess that makes sense eventually, yeah. Thanks :)

Best regards,
Marek Vasut