From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Thu, 2 Jul 2015 20:30:30 +0200 Subject: [U-Boot] [PATCH 03/11] imx: mx6ul: Update imx registers head file In-Reply-To: <1435834988-13032-4-git-send-email-Peng.Fan@freescale.com> References: <1435834988-13032-1-git-send-email-Peng.Fan@freescale.com> <1435834988-13032-4-git-send-email-Peng.Fan@freescale.com> Message-ID: <201507022030.30103.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thursday, July 02, 2015 at 01:03:00 PM, Peng Fan wrote: > Update imx register base address for i.MX6UL > > Signed-off-by: Peng Fan > Signed-off-by: Ye.Li > --- > arch/arm/include/asm/arch-mx6/imx-regs.h | 60 > ++++++++++++++++++++++---------- 1 file changed, 41 insertions(+), 19 > deletions(-) > > diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h > b/arch/arm/include/asm/arch-mx6/imx-regs.h index 35a324c..d78daac 100644 > --- a/arch/arm/include/asm/arch-mx6/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h > @@ -9,7 +9,11 @@ > > #define ARCH_MXC > > +#ifdef CONFIG_MX6UL > +#define CONFIG_SYS_CACHELINE_SIZE 64 > +#else This doesn't seem like register base at all . This is cacheline size. The patch description is thus misleading. It also fails to explain this change ... probably because UL is C-A7 ? > #define CONFIG_SYS_CACHELINE_SIZE 32 > +#endif [...] Best regards, Marek Vasut