[U-Boot] [PATCH 03/11] imx: mx6ul: Update imx registers head file

[Peng Fan <b51431@freescale.com>]

Hi Marek,

On Thu, Jul 02, 2015 at 08:30:30PM +0200, Marek Vasut wrote:
>On Thursday, July 02, 2015 at 01:03:00 PM, Peng Fan wrote:
>> Update imx register base address for i.MX6UL
>> 
>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>> Signed-off-by: Ye.Li <B37916@freescale.com>
>> ---
>>  arch/arm/include/asm/arch-mx6/imx-regs.h | 60
>> ++++++++++++++++++++++---------- 1 file changed, 41 insertions(+), 19
>> deletions(-)
>> 
>> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
>> b/arch/arm/include/asm/arch-mx6/imx-regs.h index 35a324c..d78daac 100644
>> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
>> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
>> @@ -9,7 +9,11 @@
>> 
>>  #define ARCH_MXC
>> 
>> +#ifdef CONFIG_MX6UL
>> +#define CONFIG_SYS_CACHELINE_SIZE	64
>> +#else
>
>This doesn't seem like register base at all . This is cacheline size.
>The patch description is thus misleading. It also fails to explain
>this change ... probably because UL is C-A7 ?

Will consider to split this part into a single patch, and fix in V2.

>
>>  #define CONFIG_SYS_CACHELINE_SIZE	32
>> +#endif
>[...]
>
>Best regards,
>Marek Vasut

Regards,
Peng
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