From mboxrd@z Thu Jan  1 00:00:00 1970
From: Albert ARIBAUD <albert.u.boot@aribaud.net>
Date: Wed, 15 Jul 2015 09:05:09 +0200
Subject: [U-Boot] [PATCH] nand: lpc32xx: add SLC NAND controller support
In-Reply-To: <1436905437-19149-1-git-send-email-vz@mleia.com>
References: <1436905437-19149-1-git-send-email-vz@mleia.com>
Message-ID: <20150715090509.243306f6@lilith>
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To: u-boot@lists.denx.de

Hello Vladimir,

On Tue, 14 Jul 2015 23:23:57 +0300, Vladimir Zapolskiy <vz@mleia.com>
wrote:
> The change adds support of LPC32xx SLC NAND controller.
> 
> LPC32xx SoC has two different mutually exclusive NAND controllers to
> communicate with single and multiple layer chips.
> 
> This simple driver allows to specify NAND chip timings and defines
> custom read_buf()/write_buf() operations, because access to 8-bit data
> register must be 32-bit aligned.
> 
> Support of hardware ECC calculation is not implemented (data
> correction is always done by software), since it requires a working
> DMA engine.
> 
> The driver can be included to an SPL image.

This is needed for an upcoming new board support patch, right? If so,
then I suggest you put together all patches for this new board in a
single series. This will make it clear(er) you're not adding dead code
here.

> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> Cc: Albert ARIBAUD <albert.u.boot@3adev.fr>

Amicalement,
-- 
Albert.