From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pavel Machek Date: Tue, 28 Jul 2015 22:28:39 +0200 Subject: [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init In-Reply-To: <201507281658.36313.marex@denx.de> References: <1438030335-10631-1-git-send-email-marex@denx.de> <201507281530.06958.marex@denx.de> <20150728135833.GA8480@amd> <201507281658.36313.marex@denx.de> Message-ID: <20150728202838.GA25040@amd> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi! > > + rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, > > 1); > > + /* > > + * Need to wait tMOD (12CK or 15ns) time before issuing other > > + * commands, but we will have plenty of NIOS cycles before > > actual > > + * handoff so its okay. > > + */ > > > > I don't understand this comment. > > There's plenty of code between issuing the above instruction and triggering > the mem handoff, so we don't need to add explicit delay into this function. > Also, 15nS is like 15 instructions on the SoCFPGA, so there is zero chance > we will trigger the handoff too early. What does this have to do with NIOS? CPU cores in FPGA are not mandatory, AFAICT. > > It looks much better now, thanks, > > It's far from good though and there will be another series after this one > I'm afraid. It might be even heftier, but I want to open the door to proper > SoCFPGA support this MW even if it means blowing them to shreds ... MW? Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html