From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Thu, 30 Jul 2015 13:28:00 +0200
Subject: [U-Boot] [PATCH 012/172] arm: socfpga: reset: Repair bridge
	reset handling
In-Reply-To: <55B7D64E.7000903@opensource.altera.com>
References: <1438030335-10631-1-git-send-email-marex@denx.de>
 <1438030335-10631-13-git-send-email-marex@denx.de>
 <55B7D64E.7000903@opensource.altera.com>
Message-ID: <201507301328.01000.marex@denx.de>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On Tuesday, July 28, 2015 at 09:21:50 PM, Dinh Nguyen wrote:
> On 7/27/15 3:49 PM, Marek Vasut wrote:
> > The current bridge reset code, which de-asserted the bridge reset,
> > was activelly polling whether the FPGA is programmed and ready and
> 
> s/activelly/actively
> 
> Again...only comment for this patch, no need to resend.

Fixed, thanks!

Sorry about the blast of patches . How far are you with the review please? :)

Best regards,
Marek Vasut