From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Wed, 12 Aug 2015 10:55:03 +0200
Subject: [U-Boot] [PATCH v4 2/3] mmc: dw_mmc: Support bypass mode with
	the get_mmc_clk() method
In-Reply-To: <55405834-164D-4F12-AE0F-836974B7DBF1@antoniou-consulting.com>
References: <1438913789-22308-1-git-send-email-sjg@chromium.org>
 <1438913789-22308-2-git-send-email-sjg@chromium.org>
 <55405834-164D-4F12-AE0F-836974B7DBF1@antoniou-consulting.com>
Message-ID: <201508121055.03285.marex@denx.de>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On Wednesday, August 12, 2015 at 09:39:03 AM, Pantelis Antoniou wrote:
> Hi Simon,

Hi,

> > On Aug 7, 2015, at 05:16 , Simon Glass <sjg@chromium.org> wrote:
> > 
> > Some SoCs want to adjust the input clock to the DWMMC block as a way of
> > controlling the MMC bus clock. Update the get_mmc_clk() method to support
> > this.
> > 
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> > 
> > Changes in v4:
> > - Update commit message to indicate this patch is for the dw_mmc driver
> > 
> > drivers/mmc/dw_mmc.c        |  2 +-
> > drivers/mmc/exynos_dw_mmc.c |  2 +-
> > include/dwmmc.h             | 16 +++++++++++++++-
> > 3 files changed, 17 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
> > index 8f28d7e..a034c3f 100644
> > --- a/drivers/mmc/dw_mmc.c
> > +++ b/drivers/mmc/dw_mmc.c
> > @@ -248,7 +248,7 @@ static int dwmci_setup_bus(struct dwmci_host *host,
> > u32 freq)
> > 
> > 	 * host->bus_hz should be set by user.
> > 	 */
> > 	
> > 	if (host->get_mmc_clk)
> > 
> > -		sclk = host->get_mmc_clk(host);
> > +		sclk = host->get_mmc_clk(host, freq);
> > 
> > 	else if (host->bus_hz)
> > 	
> > 		sclk = host->bus_hz;
> > 	
> > 	else {
> > 
> > diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
> > index e083745..3f702ba 100644
> > --- a/drivers/mmc/exynos_dw_mmc.c
> > +++ b/drivers/mmc/exynos_dw_mmc.c
> > @@ -39,7 +39,7 @@ static void exynos_dwmci_clksel(struct dwmci_host
> > *host)
> > 
> > 	dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
> > 
> > }
> > 
> > -unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
> > +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
> > {
> > 
> > 	unsigned long sclk;
> > 	int8_t clk_div;
> > 
> > diff --git a/include/dwmmc.h b/include/dwmmc.h
> > index 7a7555a..25cf42c 100644
> > --- a/include/dwmmc.h
> > +++ b/include/dwmmc.h
> > @@ -163,7 +163,21 @@ struct dwmci_host {
> > 
> > 	void (*clksel)(struct dwmci_host *host);
> > 	void (*board_init)(struct dwmci_host *host);
> > 
> > -	unsigned int (*get_mmc_clk)(struct dwmci_host *host);
> > +
> > +	/**
> > +	 * Get / set a particular MMC clock frequency
> > +	 *
> > +	 * This is used to request the current clock frequency of the clock
> > +	 * that drives the DWMMC peripheral. The caller will then use this
> > +	 * information to work out the divider it needs to achieve the
> > +	 * required MMC bus clock frequency. If you want to handle the
> > +	 * clock external to DWMMC, use @freq to select the frequency and
> > +	 * return that value too. Then DWMMC will put itself in bypass mode.
> > +	 *
> > +	 * @host:	DWMMC host
> > +	 * @freq:	Frequency the host is trying to achieve
> > +	 */
> > +	unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
> > 
> > 	struct mmc_config cfg;
> > 
> > };
> 
> I?m applying this now. It makes sense. No, we don?t have a clock framework
> for now so this will do.

Please don't apply patches which still have open questions, besides I still
disagree with the patch.