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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [v2 1/6] spi: cadence_qspi: move trigger base configuration in init
Date: Thu, 13 Aug 2015 04:07:20 +0200	[thread overview]
Message-ID: <201508130407.20129.marex@denx.de> (raw)
In-Reply-To: <1437013654-29387-2-git-send-email-vikas.manocha@st.com>

On Thursday, July 16, 2015 at 04:27:29 AM, Vikas Manocha wrote:

Commit message is missing.

> Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
> ---
> 
> Changes in v2: Rebased to master
> 
>  drivers/spi/cadence_qspi_apb.c |    9 ++-------
>  1 file changed, 2 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c index d053407..1ae7edf 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -534,6 +534,8 @@ void cadence_qspi_apb_controller_init(struct
> cadence_spi_platdata *plat)
> 
>  	/* Indirect mode configurations */
>  	writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
> +	writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),

You can drop the parenthesis around the first argument, they're useless.
Also, the indent of the second arg should be fixed, I believe checkpatch
might even complain about it.

> +				plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
> 
>  	/* Disable all interrupts */
>  	writel(0, plat->regbase + CQSPI_REG_IRQMASK);
> @@ -693,10 +695,6 @@ int cadence_qspi_apb_indirect_read_setup(struct
> cadence_spi_platdata *plat, /* for normal read (only ramtron as of now) */
>  		addr_bytes = cmdlen - 1;
> 
> -	/* Setup the indirect trigger address */
> -	writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> -	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
> -
>  	/* Configure the opcode */
>  	rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
> 
> @@ -790,9 +788,6 @@ int cadence_qspi_apb_indirect_write_setup(struct
> cadence_spi_platdata *plat, cmdlen, (unsigned int)cmdbuf);
>  		return -EINVAL;
>  	}
> -	/* Setup the indirect trigger address */
> -	writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> -	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
> 
>  	/* Configure the opcode */
>  	reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;

Best regards,
Marek Vasut

  reply	other threads:[~2015-08-13  2:07 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-16  2:27 [U-Boot] [v2 0/6] spi: cadence_qspi: optimize & fix indirect rd-writes Vikas Manocha
2015-07-16  2:27 ` [U-Boot] [v2 1/6] spi: cadence_qspi: move trigger base configuration in init Vikas Manocha
2015-08-13  2:07   ` Marek Vasut [this message]
2015-08-13 15:50     ` vikasm
2015-08-13 17:35       ` Marek Vasut
2015-08-13 19:05         ` vikasm
2015-08-14  1:24         ` vikas
2015-08-14  1:43           ` Marek Vasut
2015-08-14  1:44             ` vikas
2015-08-14  1:55               ` Marek Vasut
2015-07-16  2:27 ` [U-Boot] [v2 2/6] spi: cadence_qspi: remove sram polling from flash read Vikas Manocha
2015-08-13  2:09   ` Marek Vasut
2015-08-13 16:27     ` vikasm
2015-08-13 17:33       ` Marek Vasut
2015-08-13 19:49         ` vikas
2015-08-13 20:35           ` Marek Vasut
2015-08-13 21:04             ` vikas
2015-08-13 22:47               ` Marek Vasut
2015-08-13 23:18                 ` vikas
2015-08-13 23:46                   ` Marek Vasut
2015-08-14  0:26                     ` vikas
2015-08-14  0:44                       ` Marek Vasut
2015-08-14  0:46                         ` vikas
2015-08-14  1:03                           ` Marek Vasut
2015-08-14  1:05                             ` vikas
2015-08-14  3:54                               ` Marek Vasut
2015-07-16  2:27 ` [U-Boot] [v2 3/6] spi: cadence_qspi: remove sram polling from flash write Vikas Manocha
2015-08-13  2:11   ` Marek Vasut
2015-08-13 16:30     ` vikasm
2015-08-13 17:34       ` Marek Vasut
2015-07-16  2:27 ` [U-Boot] [v2 4/6] spi: cadence_qspi: fix indirect read/write start address Vikas Manocha
2015-07-16  2:27 ` [U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address & transfer " Vikas Manocha
2015-08-13  2:15   ` Marek Vasut
2015-08-13 16:42     ` vikasm
2015-08-13 21:36       ` vikas
2015-08-13 22:48         ` Marek Vasut
2015-08-14  0:37           ` vikas
2015-08-14  1:04             ` Marek Vasut
2015-08-14  1:39               ` vikas
2015-08-14  1:56                 ` Marek Vasut
2015-08-14  2:14                   ` Vikas MANOCHA
2015-07-16  2:27 ` [U-Boot] [v2 6/6] spi: cadence_qspi: get fifo width from device tree Vikas Manocha

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