[U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address & transfer start address

[Marek Vasut <marex@denx.de>]

On Friday, August 14, 2015 at 02:37:53 AM, vikas wrote:
> Hi,
> 
> On 08/13/2015 03:48 PM, Marek Vasut wrote:
> > On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote:
> >> Hi Marek,
> > 
> > Hi!
> > 
> >> On 08/13/2015 09:42 AM, vikasm wrote:
> >>> Hi Marek,
> >>> 
> >>> On 08/12/2015 07:15 PM, Marek Vasut wrote:
> >>>> On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote:
> >>>>> This patch is to separate the base trigger from the read/write
> >>>>> transfer start addresses.
> >>>> 
> >>>> This patch breaks the QSPI support on SoCFPGA.
> >>> 
> >>> ok, can you please try to debug the issue. Logically this patch looks
> >>> good to me unless there is something specific to socfpga.
> >> 
> >> One quick check, can you test if it works on reverting the trigger base
> >> in arch/arm/dts/socfpga.dtsi from <0x00000000 0x0010> to <0xffa00000
> >> 0x1000>.
> > 
> > Can you please spin V3 of the patchset first, one which omits the buggy
> > bits, so I can test it on a more final form of the patches ? Please keep
> > me on CC, I'll test it then.
> 
> Once i add sram level test patches, i would not be able to test it on my
> platform. This particular issue is pending for long time. I suggest to
> debug (at least with above mentioned quick test) this particular
> issue/patch with current version v2. There is only minor change (format
> string) in this patch for v3.

That's fine, just send the V3 as RFT and I'll check it.

Best regards,
Marek Vasut